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fedl7396a/b/e-07 issue date: jan. 15, 2015 ml7396a/b/e sub ghz band short range wireless transceiver ic overview the ml7396 family (ml7396a (915mhz band), ml7396b (920mhz band), and ml7396e (868mhz band)) are ics for transmitting/receiving data which integrate the rf, if, modem an d host interface sections into one chip for the specified low power radio communication. the ml7396 family is used for fcc part15, arib std-108(specified low-power radio station, 920mhz-band telemeter, telecontrol and data transmission radio equipment), etsi en 300 220 compliant radio station, and uses a packet transmission function of ieee802.15.4d and ieee802.15.4g. features ? compliant to arib std t-108 (ml7396b) ? compliant to fcc part15 (ml7396a) ? compliant to etsi en 300-220 (ml7396e) ? high resolution modulation by using fractional-n pll direct modulation. ? modulation: gfsk / gmsk, fsk / msk (msk is fsk transmission of modulation index: m=0.5 ) ? data rates: 10 / 20 / 40 / 50 / 100 / 150 / 200 kbps and 400 kbps (option) ? data coding: nrz and manchester codes ? programable channel filter suited to data rates ? programmable frequency deviation function ? tx and rx data inverse function ? 36mhz oscillator circuit ? tcxo direct inputs available ? oscillator capacitance fine tuning function ? frequency fine tuning function (using fractional-n pll) ? synchronous serial peripheral interface (spi) ? on chip tx pa (20mw/10mw/1mw selectable) ? external tx pa control function ? rssi indicator and threshold judgement function ? afc function ? antenna diversity function ? test pattern generator (pn9, cw, 01 pattern, all?1?, all?0?) ? fec function ? crc32 (note: this function is not compliant to ieee802.15.4g.) ? ieee802.15.4d/g support o two 256-byte fifos (tx/rx common use) o max packet length 2047 byte (ieee802.15.4g mode) o rx preamble pattern detection function (programmable between 1 to 15 byte) o programmable tx preamble length (max 255 byte) o sfd generation and detection function (max 4 byte) o programmable crc function (crc32, crc16-ibm, crc16, crc8 or no-crc) o whitening function o address filtering function o automatic acknowledge (ack tx or rx) function o fec function (ieee802.15.4g mode) note; interleaving mode is not compliant to ieee802.15.4g. 1/140
fedl7396a/b/e-07 ml7396a/b/e 2/140 ? supply voltage: 1.8 to 3.6v (tx power 1mw mode) 2.3 to 3.6v (tx power 10mw mode) 2.6 to 3.6v (tx power 20mw mode) ? operating temperature: -40 to +85 ? c ? current consumption (920mhz) sleep mode 0.6 a (typ.) (registor value retention) idle mode 1.4ma (typ.) tx 20mw 32 ma (typ.) 10mw 24 ma (typ.) 1mw 13 ma (typ.) rx 15 ma (typ.) (@100kbps) ? package 40 pin wqfn p-wqfn40-0606-0.50 pb free, rohs compliant description convention 1) numbers description ?0xnn? indicates hexa decimal. ?0bnn? indicates binary. example: 0x11= 17(decimal), 0b11= 3(decimal) 2) registers description [: b ] register example: [clk_set:b0 0x02] register register name: clk_set bank no: 0 register address: 0x02 3) bir name description ([: b ()]) example: rate[2:0] ([data_set:b0 0x47(2-0)]) bit name: rate[2:0] register name: data_set bank no: 0 register address: 0x47 bit location: bit2 to bit0 4) in this document ?tx? stands for transmittion. ?rx? stands for reception.
fedl7396a/b/e-07 ml7396a/b/e 3/140 block diagram lna mix bpf limiter pa 1mw/10m w/20mw lo pll demod v co digital mod rf host mcu lc ml7396a_b_e dmon (clkout) rf_ma nager s p i dclk dio temp phy fmap trx_sw rssi ed_val fifo reg_out reg_core xin xout dio i r c bb sclk sdo sdi scen sintn a nt_sw v bg resetn a_mon tcxo dcnt a nt_sw lna_p pa_out reg(pa) reg reg_pa regpdin atest1 atest2 v b_ext lp1,2 ind1,2
fedl7396a/b/e-07 ml7396a/b/e 4/140 pin configuration 40 pin wqfn lna_p vdd_pa reg_pa pa_out atest2 atest1 a_mon vdd_if dcnt trx_sw 30 29 28 27 26 25 24 23 22 21 n.c. 31 20 ant_sw vdd_rf 32 19 test lp1 33 18 vddio vdd_cp 34 17 dmon lp2 35 16 dclk ind1 36 15 dio ind2 37 14 vddio vb_ext 38 13 sdi vdd_vco 39 12 scen vdd_reg 40 11 sclk 12345678910 vbg reg_out reg_core xin xout tcxo resetn regpdin sdo sintn j? pkg y gnd (t.b.d.) j? pkg y gnd gnd pa d note) gnd pad in the middle of the ic is reverse side (name: gnd pad)
fedl7396a/b/e-07 ml7396a/b/e 5/140 pin definitions symbols i rf : rf input o rf : rf output i a : analog input i os : oscillator input o os : oscillator output i : digital input o : digital output i/o : digital inout is : schmitt trigger input rf and analog pins pin no pin name reset state i/o active level detail function 30 lna_p i i rf - rf antenna input 27 pa_out o o rf - rf antenna output 36 ind1 - - - pin for vco inductor 37 ind2 - - - pin for vco inductor 33 lp1 - - - pin for pll loop filter 38 vb_ext - - - pin for smoothing capacitor for internal bias 25 atest1 hi-z o rf - test pin for analog circuit. *left open when in normal use 26 atest2 hi-z o rf - test pin for analog circuit. *left open when in normal use 24 a_mon hi-z o rf - analog monitor pin (*1) [description] *1 analog monitor signal can be configured by [rssi/temp_out:b1 0x03] register, no signal assigned as default condition.
fedl7396a/b/e-07 ml7396a/b/e 6/140 pin definition(continued) spi interface pins pin no pin name reset state i/o active level detail function 9 sdo o/l o h or l spi data output 13 sdi i is h or l spi data input 11 sclk i is p or n spi clock input 12 scen i is l spi chip enable l: enable h: disable 10 sintn o/h o l spi interrupt output l: interrupt occurs h: - dio interface pins pin no pin name reset state i/o active level detail function 15 dio o/l i/o h or l dio data input/output 16 dclk o/l o p or n dio clock output regulator pins pin no pin name reset state i/o active level detail function 2 reg_out - - - regulator output (typ.1.5v) (cap 10uf) note: this pin will output 0v in the sleep state 3 reg_core - - - monitor pin for power supply to digital core(typ.1.5v) (cap 10uf) 1 vbg - - - pin for decoupling capacitor pin (cap 0.1uf) 8 regpdin i i h power down pin for regulator * fix to ?l? for normal use 28 reg_pa - - - regulator output for pa block note: this pin will output 0v in the sleep state
fedl7396a/b/e-07 ml7396a/b/e 7/140 pin definition(continued) miscellaneous pins pin no pin name reset state i/o active level detail function 7 resetn i is l hardware reset l: hardware reset enable h: normal operation 4 xin i ios p or n 36mhz crystal pin1 *fixed to gnd in case of using external clock 5 xout o oos p or n 36mhzcristal pin2 *fixed to gnd in case of using external clock 6 tcxo i i a - external clock (tcxo) input pin. *fixed to gnd in case of using crystal oscillator 20 ant_sw o/l o h or l or od diversity control signal 21 trx_sw o/l o h or l or od tx-rx switch signal 19 test i i h test mode input fixed to ?l? for normal use 17 dmon*1 o o h digital monitor pin primary function: clock output (6mhz) secondary function: pll_ld output third function: fifo trigger output 22 dcnt o/l o h or l or od external tx pa control signal 31,35 n.c. - - - non connection [description] *1 function of dmon pin can be selected by following condition. clock output as a default. if clock output is not used, please select another function. please refer to each register description for more details. primary function will have higher priority when multiple function are configured simultaneously. configuration of dmon output function name configuration register name address bit position (bit symbol) clk output clk_set b0 0x02 bit4 (clkout_en) pll_ld output pll_mon/dio_sel b0 0x69 bit4 (pll_ld) fifo trigger output crc_area/fifo_trg b0 0x77 bit0 (fifo_trg_en)
fedl7396a/b/e-07 ml7396a/b/e 8/140 power supply pins pin no pin name reset state i/o active level detail function 14,18 vddio -/- pwr - power supply for digital ios (input voltage: 1.8v to 3.3v) 40 vdd_reg -/- pwr - power supply for regulator input (input voltage: 1.8v to 3.3v) 29 vdd_pa -/- pwr - power supply for pa block (input voltage: 1.8v to.3.3v, depending on tx mode) 32 vdd_rf -/- pwr - power supply for rf blocks (reg_out is connected, typ.1.5v) 23 vdd_if -/- pwr - power supply for if block (reg_out is connected, typ.1.5v) 34 vdd_cp -/- pwr - power supply for charge pump (reg_out is connected, typ.1.5v) 39 vdd_vco -/- pwr - power supply for vco (reg_out is connected, typ.1.5v) el - -/- gnd - gnd pad unused pins unused pins treatments are as follows: pin name pin number recommended treatment xin 4 fixed to gnd (when tcxo is used) xout 5 fixed to gnd (when tcxo is used) tcxo 6 fixed to gnd (when crystal osc is used) atest1 25 left open atest2 26 left open a_mon 24 left open ant_sw 20 left open dmon 17 left open *1 dcnt 22 left open *1 if not using dmon, it is necessary to stop clock out (default output on dmon) by clkout_en ([clk_set:b0 0x02(4)]). left open with enableing clock out causes the perfoemance down on rx sensitivity. note: if input pins are high-impedence state and leave open, excess current could be drawn. care must be taken that unused input pins and unused i/o pins should not be left open.
fedl7396a/b/e-07 ml7396a/b/e 9/140 electrical characteristics absolute maximum ratings item symbol condition rating unit power supply (i/o) (*1) v ddio -0.3 to +4.6 v power supply (rf) (*2) v ddrf -0.3 to +2.0 v digital input voltage v din -0.3 to v ddio +0.3 v rf input voltage v rfin -1.0 to +2.0 v analog input voltage v ain -0.3 to v ddio +0.3 v analog input voltage2 (*3) v ain2 -0.3 to v ddrf +0.3 v tcxo input voltage v tcxo -0.3 to +1.75 v digital output voltage v do ta=-40 to 85 ?c -0.3 to v ddio +0.3 v rf output voltage v rfo gnd=0v -0.3 to v ddrf +1.9 v analog output voltage v ao -0.3 to v ddio +0.3 v analog output voltage2 (*4) v ao2 -0.3 to v ddrf +0.3 v digital input current i di -10 to +10 ma rf input current i rf -2 to +2 ma analog input current i ai -2 to +2 ma analog input current2 (*3) i ai2 -2 to +2 ma tcxo input current i tcxo -2 to +2 ma digital output current i do -8 to +8 ma rf output current i rfo -2 to +60 ma analog output current i ao -2 to +2 ma analog output current2 (*4) i ao2 -2 to +2 ma power dissipation p d ta=+25 ? c 300 mw storage temperature t stg - -55 to +150 ?c *1 vdd_io, vdd_reg, vdd_pa pins *2 vdd_rf, vdd_if, vdd_vco, vdd_cp pins *3 xin, tcxo pins *4 xout pin
fedl7396a/b/e-07 ml7396a/b/e 10/140 recommended operating conditions item symbol conditions min typ max unit power supply (i/o) v ddio vdd_io, vdd_reg pins 1.8 3.3 3.6 v vdd_pa pin tx power 1mw mode 1.8 3.3 3.6 v vdd_pa pin tx power 10mw mode 2.3 3.3 3.6 v power supply (pa) v ddpa vdd_pa pin tx power 20mw mode 2.6 3.3 3.6 v power supply (rf) (*2) v ddrf vdd_rf, vdd_if, vdd_vco, vdd_cp pins 1.4 1.5 1.6 v operating temperature t a - -40 +25 +85 ?c digital input rising time t ir digital input pins (*1) - - 20 ns digital input falling time t if digital input pins (*1) - - 20 ns digital output loads c dl all digital output pins - - 20 pf master clock1 accuracy (crystal) f mck1 xin, xout pins -20ppm (*3) 36 +20ppm (*3) mhz master clock2 accuracy (tcxo) f mck2 tcxo pin -20ppm (*3) 36 +20ppm (*3) mhz tcxo input voltage v tcxo dc cut 0.8 - 1.5 vpp spi clock frequency f sclk sclk pin 0.032 2 16 mhz spi clock duty ratio d sclk sclk pin 45 50 55 % rf channel frequency f rf lna_p,pa_out pins 863 - 960 mhz *1 those pins with symbol i, is at pin definition section *2 use reg_out output of this lsi. *3 it?s max.+10ppm and min.-10ppm at 10kbps setting. [note] electrical characteristics are in the above recommended operating conditions without special instruction.
fedl7396a/b/e-07 ml7396a/b/e 11/140 * following ?typ? value is not guaranteed value studied variation of ic but typical centre value. power consumption item symbol conditions min typ (*2) max unit idd1 sleep state (retaining register values) - 0.6 3.0(*3) a idd2 idle state - 1.4 3.0 ma idd3 rf rx state (*4) - 15.0 20.0 ma idd4 rf tx state (1mw) (*4) - 13.0 20.0 ma idd5 rf tx state (10mw) (*4) - 24.0 35.0 ma power consumption (*1) idd6 rf tx state (20mw) (*4) - 32.0 43.0 ma *1 power consumption is sum of current consumption of all power supply pins *2 ?typ? value is centre value under condition of vddio=3.3v, 25 ? c. *3 this ?max? value is under condition of 25 ? c. other ?max? values are defind under recommended operating coditions. *4 current consumption when the data rate is 100kbps and the rf frequency is 920mhz.
fedl7396a/b/e-07 ml7396a/b/e 12/140 dc characteristics item symbol conditions min typ (*2) max unit vih1 digital input/inout pins v ddio * 0.75 - v ddio v voltage input high vih2 xin pin v ddrf *0.9 - v ddrf v vil1 digital input/inout pins 0 - v ddio *0.18 v voltage input low vil2 xin pin 0 - v ddrf *0.1 v schmitt trigger threshold high level vt+ resetn pin sdi, sclk, scen pins - 1.2 v ddio *0.75 v schmitt trigger threshold low level vt- esetn pin sdi, sclk, scen pins v ddio *0.18 0.8 - v iih1 digital input/inout pins -1 - 1 a iih2 xin pin -0.3 - 0.3 a iil1 digital input/inout pins -1 - 1 a input leakage current iil2 xin pin -0.3 - 0.3 a iozh1 digital inout pins -1 - 1 a tri-state output leakage current iozl1 digital inout pins -1 - 1 a voltage output level h voh ioh=-4ma /-2ma (*1) v ddio *0.8 - v ddio v voltage output level l vol iol=4ma /2ma (*1) 0 - 0.3 v sleep state 0.95 1.3 1.65 v regulator output voltage reg_core (*2) other states 1.40 1.5 1.60 v cin input pins - 6 - pf cout output pins - 9 - pf crfio rf inout pins - 9 - pf pin capacitance cai analog input pins - 9 - pf *1 dmon pin is ioh=-2ma/2ma *2 reg_core pin and reg_out pin. reg_out pin becomes 0v when in sleep state.
fedl7396a/b/e-07 ml7396a/b/e 13/140 rf characteristics data rate : 10kbps/ 20kbps/ 40kbps/ 50kbps/100kbps/ 150kbps/200kbps/ 400kbps modulation scheme : gfsk channel spacing : 200khz/400khz/600khz frequency : support 750mhz to 1ghz by changing l/c components between ind1 and ind2 pins others : definition point is a antenna connector in the reference circuit. rf characteristics out of below table include 400kbps (option) are available as reference data separately. [tx] item condition min typ max unit 20mw (13dbm) mode 9 13 15 dbm 10mw (10dbm) mode 6 10 12 dbm tx power 1mw (0dbm) mode -4 0 2 dbm frequency deviation setting range [fdev] (*1) - - 2,250 khz 920mhz band (920.5mhz to 928.1mhz) occupied bandwidth n : number of channel - - 200 * n khz 20mw mode (920.5mhz to 922.3mhz) - - -7 dbm 10mw mode - - -10 dbm power at channel edge 1mw mode - - -20 dbm 20mw mode 1ch, bandwidth 200khz) - -33 -15 dbm 10mw mode +/-1ch bandwidth: 200khz - -39 -18 dbm adjacent channel power 1mw mode +/-1ch bandwidth: 200khz - -47 -26 dbm 710mhz or lower, 100khz band - -65 -36 dbm higher than 710mhz to 900mhz, 1mhz band - -70 -55 dbm higher than 900mhz to 915mhz, 100khz band - -72 -55 dbm higher than 915mhz to 930mhz, 100khz band (excluding within 200 + 100*n khz above and below the channel frequency, however, within 100 + 100*n khz above and below for 920.5mhz to 922.3mhz. n is the number of concurrently used channels) - -51 -36 dbm higher than 930mhz to 1000mhz, 100khz band - -70 -55 dbm higher than 1000mhz to 1215mhz, 1mhz band - -75 -45 dbm spurious emission level (20mw mode) higher than 1215mhz, 1mhz band (2nd harmonics or higher) - -40 -30 dbm 915mhz band (902mhz to 928mhz) 6db bandwidth frequency deviation=171khz 500 - - khz power spectrum density 20mw mode, frequency deviation = 171khz, 3khz band - - 8 dbm 900mhz or lower - -65 -56 dbm spurious emission level (20mw mode) higher than 960mhz (2nd harmonics or higher) - -50 -41 dbm 868mhz band (863mhz to 870mhz) (*2) spurious emission level (10mw mode) higher than 1000mhz (2nd harmonics or higher) - -35 -30 dbm *1 while the setting range is described as above, the possible maximum value depends on the rf channel frequency to be used. rf channel frequency frequency deviation should not include a multiple of 36mhz (864mhz, 900mhz, 936mhz, and so on). example) for 902mhz, 2,000khz is a possible maximum frequency deviation value. *2 863.5mhz to 866.2mhz cannot be used. for details, refer section "programing channel frequency."
fedl7396a/b/e-07 ml7396a/b/e 14/140 [rx] item condition min typ max unit 920mhz band (920.5mhz to 928.1mhz) 50kbps mode (*1) - -108 -102 dbm 100kbps mode (*1) - -106 -100 dbm minimum rx sensitivity ber<0.1% 200kbps mode (*1) - -102 -97 dbm maximum input level 50kbps mode/100kbps mode/200kbps mode 0 - - dbm 50kbps mode 20 35 - db 100kbps mode 20 35 - db adjacent channel selectivity 200kbps mode 20 35 - db 50kbps mode 30 45 - db 100kbps mode 30 45 - db alternate channel selectivity 200kbps mode 30 45 - db minimum energy detection level [ed value] - - -100 dbm energy detection range dynamic range 60 70 - db energy detection accuracy -6 - +6 db 710mhz or lower, 100khz band - <-93 -54 dbm higher than 710mhz to 900mhz, 1mhz band - <-83 -55 dbm higher than 900mhz to 915mhz, 100khz band - <-93 -55 dbm higher than 915mhz to 930mhz, 100khz band - -63 -54 dbm higher than 930mhz to 1000mhz, 100khz band - <-93 -55 dbm spurious emission level arib t108 measurement condition 915.9mhz 916.9mhz 920.5mhz 929.7mhz higher than 1000mhz - -57 -47 dbm 915mhz band (902mhz to 928mhz) 100kbps mode (modulation index = 1) (*1) - -106 -99 dbm 150kbps mode (modulation index = 0.5) (*1) - -102 -96 dbm 200kbps mode (modulation index = 1) (*1) - -102 -96 dbm 100kbps mode (frequency shift: 171khz) - -100 -87 dbm 150kbps mode (frequency shift: 171khz) - -97.5 -84 dbm minimum receiver sensitivity ber<0.1% 200kbps mode (frequency shift: 171khz) - -96.5 -83 dbm 868mhz band (863mhz to 870mhz) (*2) 50kbps mode (*1) - -108 -102 dbm 100kbps mode (*1) - -106 -100 dbm minimum receiver sensitivity ber<0.1% 200kbps mode (*1) - -102 -97 dbm 1000mhz or lower (local frequency) - -63 -57 dbm collateral emission level higher than 1000mhz - -57 -47 dbm *1 when nbo_sel([data_set:b0 0x47(7)])=0b0. *2 863.5mhz to 866.2mhz cannot be used. for details, refer section "programing channel frequency."
fedl7396a/b/e-07 ml7396a/b/e 15/140 spi interface characteristics item symbol condition min typ max unit sclk clock frequency f sclk 0.032 2 16 mhz scen input setup time t ssnsu 30 - - ns scen input hold time t ssnh 30 - - ns sclk high pulse width t wsckh 28 - - ns sclk low pulse width t wsckl 28 - - ns sdi input setup time t sdisu 5 - - ns sdi input hold time t sdih 15 - - ns scen negate interval t ssnai 60 - - ns sdo output delay time t sdo load capacitance cl=20pf - - 22 ns [note] all timing parameter is defined at voltage level of v ddio * 20% and v ddio * 80%. sce sclk msb in bits6-1 lsb in t ssnh bits6-1 t sdo msb out t wsckl t wsckh t sdisu t sdih f sclk t ssnsu sdi lsb out sdo t ssnai sce
fedl7396a/b/e-07 ml7396a/b/e 16/140 dio interface characteristics item symbol condition min typ max unit dio input setup time t disu 1 - - s (rising edge synchronization) dio input setup time t disu2 0 - - s (falling edge synchronization) dio input hold time t dih 0 - - ns (rising edge synchronization) 10 dio input hold time (*3) t dih2 5 - - s (falling edge synchronization) 2.5 dio output hold time t doh 20 - - ns load capacitance cl=20pf 50 dclk frequency (*1) (*3) (tx) f dclk1 -20ppm 100 +20ppm khz 200 dclk frequency (*2) (*3) (rx) f dclk2 -4% 50 100 +4% khz 200 dclk output duty ratio (tx) d dclk - 50 - % 40 60 - % dclk output duty ratio (rx) d dclk *1 dclk clock frequency in tx mode will be varied depending on the variance of master clock frequency. *2 dclk clock frequency in rx mode will be varied by reproduced clock and its jitter. *3 these characteristics are depend on the settin g to the rate [2:0] ([data_set:b0 0x47(2-0)]. (upper: 50kbps, mid: 100kbps, lower: 200kbps) [note] all timing parameter is defined at voltage level of v ddio * 20% and v ddio * 80% (*1) (*1) dclk dio (input) rising edge sy nc hr oniz a tio n valid valid dio(output) valid valid valid t doh dio (input) falling edge s y nchronization valid valid t disu2 t dih2 valid valid(*2) t disu t dih f dclk1 / f dclk2 (*1) (*1) valid (*1) timing when ml7396 takes the dio input. (*2) for the falling edge synchronization, the first two bits of dio input have the same data, refer section ?tx mode (with di o mode)?
fedl7396a/b/e-07 ml7396a/b/e 17/140 clock output characteristics clock output can be controled by [clk_set:b0 0x02] register (initial value:enable), clock output from dmon pin. item symbol condition min typ max unit clock output frequency f clkout - 0.0088 6 36 mhz 12mhz 30 - 70 % load capacitance cl=20pf clock output duty ratio d clkout (*1) other than above 48 50 52 % *1 duty ratio will be h:l = 1:2 when output frequency is 12mhz.. refer [clk_out: b0 0x03] register (). f clkout dmon reset item symbol condition min typ max unit all power supply pins resetn delay time (power on) t rdl 1.5 - - ms (after power on) resetn pulse period t rpw 200 - - ns (when starting from vddio=0v) resetn pulse period 2 (*1) t rpw2 1.5 - - ms vdd>1.8v (when starting from vddio 0v) resetn rising period t rrst - - 1 ms vdd level gnd level vddio t rpw t rpw2 resetn t rdl t rrst (*1) when starting from vddio .0v, input a pulse to the rese tn signal after vddio exceeds 1.8v.
fedl7396a/b/e-07 ml7396a/b/e 18/140 power on sequence item symbol condition min typ max unit power on state power on time t pwon - - 5 ms (all power supply pins) 80% 20% t pwon vdd level gnd level vdd
fedl7396a/b/e-07 ml7396a/b/e 19/140 registers register map it is consist of 3bank, bank0, bank1, bank2. each bank ha s address space of 0x00 to 0x7f, 128 byte in total. the space shown as gray highlighted part is not implemented in lsi or reserved bits. tx/rx fifo is implemented in phy block, those register except for fifo is implemented in spi block. the address not exist in the memory map is not accessible. also, the address is not accessible during the vco calibration. in each bank, there are some registers that can not be access unless give access allowance by tst_acen ([bank_sel: b0/b1/b2 0x00(7)] =0b1. such registers are marked with ?#? in the following list. the tst_acen enable setting is required in the initial setting or test mode setting, but it is recommended to set disable when in normal operation to avoid miss-setting. for registers whose setting value is specified by the ?ml7396f amily_initialregistersetting? file, please set the value shown in the file. : implemented as functionable register : implemented as reserved bits
fedl7396a/b/e-07 ml7396a/b/e 20/140 bank0 bit address symbol (# test register) 7 6 5 4 3 2 1 0 description 0x00 bank_sel register access bank selection 0x01 rst_set software reset setting 0x02 clk_set clock configuration 0x03 clkout clkout frequency setting 0x04 rate_set1 data rate conversion setting 1 0x05 rate_set2 data rate conversion setting 2 0x06-0x07 reserved reserved 0x08 #adc_clk_set rssi adc clock frequency setting 0x09-0x0a reserved reserved 0x0b #osc_adj load capacitor adjustment for oscillation circuit 0x0c #rf_test_mode tx test pattern setting 0x0d-0x0e reserved reserved 0x0f # phy_state phy status indication 0x10 #fifo_bank fifo bank indication 0x11 #pll_lock_detect pll lock detection configuration 0x12 cca_ignore_level ed threshold level setting for excluding cca judgement 0x13 cca_level cca threshold level setting 0x14 cca_abort timing setting for forced termincation of cca operation 0x15 cca_cntrl cca control setting and result indication 0x16 ed_rslt ed (energy detection) value indication 0x17 idle_wait_l idle detection period setting during cca (low 8bits) 0x18 idle_wait_h idle detection period setting during cca (high 2bits) 0x19 cca_prog_l idle judgement elapsed time indication during cca (low byte) 0x1a cca_prog_h idle judgement elapsed time indication during cca (high 2bits) 0x1b ed_cntrl ed detection control setting 0x1c gain_mtol threshold level setting for switching middle gain to low gain 0x1d gain_ltom threshold level setting for switching low gain to middle gain 0x1e gain_htom gain update setting and threshold level setting for switching high gain to middle gain 0x1f gain_mtoh threshold level setting for switching middle gain to high gain 0x20 rssi_adj_m rssi offset value setting during middle gain operation 0x21 rssi_adj_l rssi offset value setting during low gain operation 0x22 rssi_stable_time time parameter for rssi value become stable after gain switch 0x23 rssi_val_adj rssi scale factor setting for ed value conversion. 0x24 int_source_grp1 fifo clear setting and interrupt status for int00 to int05 0x25 int_source_grp2 interrupt status for int08 to int15 0x26 int_source_grp3 interrupt status for int16 to int23 0x27 int_source_grp4 interrupt status for int24 and int25 0x28 pd_data_req data transmission request status indication 0x29 pd_data_ind data reception status indication 0x2a int_en_grp1 interrupt mask for int00 to int05 0x2b int_en_grp2 interrupt mask for int08 to int15 0x2c int_en_grp3 interrupt mask for int16 to int23 0x2d int_en_grp4 interrupt mask for int24 and int25 0x2e ch_en_l rf channel enable setting for low 8ch 0x2f ch_en_h rf channel enable setting for high 8ch 0x30 if_freq_afc_h if frequency setting during afc operation (high byte) 0x31 if_freq_afc_l if frequency setting during afc operation (low byte) 0x32 bpf_afc_adj_h bandpass filter capacitance adjustment during afc operation (high 2bits) 0x33 bpf_afc_adj_l bandpass filter capacitance adjustment during afc operation (low byte) 0x34 afc_cntrl afc control setting 0x35 tx_alarm_lh tx fifo full level setting 0x36 tx_alarm_hl tx fifo empty level setting 0x37 rx_alarm_lh rx fifo full level setting
fedl7396a/b/e-07 ml7396a/b/e 21/140 bank0 (continued) bit address symbol (# test register) 7 6 5 43210 description 0x38 rx_alarm_hl rx fifo empty level setting 0x39 preamble_set preamble pattern setting 0x3a sfd1_set1 sfd pattern #1 1 st byte setting (max 4byte) 0x3b sfd1_set2 sfd pattern #1 2 nd byte setting (max 4byte) 0x3c sfd1_set3 sfd pattern #1 3 rd byte setting (max 4byte) 0x3d sfd1_set4 sfd pattern #1 4 th byte setting (max 4byte) 0x3e sfd1_set1 sfd pattern #2 1 st byte setting (max 4byte 0x3f sfd2_set2 sfd pattern #2 2 nd byte setting (max 4byte) 0x40 sfd2_set3 sfd pattern #2 3 rd byte setting (max 4byte) 0x41 sfd2_set4 sfd pattern #2 4 th byte setting (max 4byte) 0x42 tx_pr_len tx preamble length setting 0x43 rx_pr_len/sfd_len rx preamble setting and sfd length setting 0x44 sync_condition bit error toleran ce setting in rx preamble and sfd detection 0x45 packet_mode_set packet configuration 0x46 fec/crc_set fec and crc configuration 0x47 data_set data configuration 0x48 ch0_fl channel #0 frequency (f-counter) setting (low byte) 0x49 ch0_fm channel #0 frequency (f-counter) setting (middle byte) 0x4a ch0_fh channel #0 frequency (f-counter) setting (high 4bits) 0x4b ch0_na channel #0 frequency (n-counter and a-counter) setting 0x4c ch_space_l channel space setting (low byte) 0x4d ch_space_h channel space setting (high byte) 0x4e f_dev_l gfsk frequency deviation setting (low byte ) 0x4f f_dev_h gfsk frequency deviation setting (high byte) 0x50 ack_timer_l ack timer setting (low byte) 0x51 ack_timer_h ack timer setting (high byte) 0x52 ack_timer_en ack timer control setting 0x53 ack_frame1 ack frame control field (2bytes) setting (low byte) 0x54 ack_frame2 ack frame control field (2bytes) setting (high byte) 0x55 auto_ack_set auto_ack function setting 0x56-x58 reserved reserved 0x59 gfil00 / fsk_fdev1 gaussian filter coefficient setting 1 / fsk 1 st frequency deviation setting 0x5a gfil01 / fsk_fdev2 gaussian filter coefficient setting 2 / fsk 2 nd frequency deviation setting 0x5b gfil02 / fsk_fdev3 gaussian filter coefficient setting 3 / fsk 3 rd frequency deviation setting 0x5c gfil03 / fsk_fdev4 gaussian filter coefficient setting 4 / fsk 4 th frequency deviation setting 0x5d gfil04 gaussian filter coefficient setting 5 0x5e gfil05 gaussian filter coefficient setting 6 0x5f gfil06 gaussian filter coefficient setting 7 0x60 gfil07 gaussian filter coefficient setting 8 0x61 gfil08 gaussian filter coefficient setting 9 0x62 gfil09 gaussian filter coefficient setting 10 0x63 gfil10 gaussian filter coefficient setting 11 0x64 gfil11 gaussian filter coefficient setting 12 0x65 fsk_time1 fsk 3 rd frequency deviation (fdev3) hold time setting 0x66 fsk_time2 fsk 2 nd frequency deviation (fdev2) hold time setting 0x67 fsk_time3 fsk 1 st frequency deviation (fdev1) hold time setting 0x68 fsk_time4 fsk no-deviation frequency (carrier frequency) hold time setting
fedl7396a/b/e-07 ml7396a/b/e 22/140 bank0 (continued) bit address symbol (# test register) 7 6 5 4 3 2 1 0 description 0x69 pll_mon/dio_sel pll lock detection signal output control and dio mode configuration 0x6a fast_tx_set tx trigger level setting in fast_tx mode 0x6b ch_set rf channel setting 0x6c rf_status rfstate setting and status indication 0x6d 2div_ed_avg average number setting for ed calculation during 2 diversity 0x6e 2div_gain_cntrl gain control setting during 2 diversity 0x6f 2div_search 2 divers ity search mode and search time setting 0x70 2div_fast_lv ed threshol d level setting during 2 diversity fast mode 0x71 2div_cntrl 2 diversity setting 0x72 2div_rslt 2 diversity resurt indication and forced antenna control setting 0x73 ant1_ed acquired ed value by antenna 1 0x74 ant2_ed acquired ed value by antenna 2 0x75 rf_cntrl_set rf control pin configuration (ant_sw, trx_sw,dcnt) 0x76 reserved reserved 0x77 crc_area/fifo_trg crc calculation field and fifo trigger setting 0x78 rssi_mon rssi value indication 0x79 temp_mon temperature indication 0x7a pn9_set_l pn9 initialized status setting / randum number indication (low byte) 0x7b pn9_set_h pn9 initialized status setting / randum number indication (high 1bit) and pn9 enable control 0x7c rd_ fifo_last fifo remaining size or fifo address indication 0x7d reserved reserved 0x7e wr_tx_fifo tx fifo 0x7f rd_rx_fifo rx fifo bank1 bit address symbol 7 6 5 4 3 2 1 0 description 0x00 bank_sel register access bank selection 0x01 demod_set demodulator setting 0x02 rssi_adj rssi value adjustment 0x03 rssi/temp_out rssi and temperature data output setting 0x04 pa_adj1 pa adjustment 1 st setting 0x05 pa_adj2 pa adjustment 2 nd setting 0x06 pa_adj3 pa adjustment 3 rd setting 0x07 pa_cntrl external pa control and pa mode setting 0x08 sw_out/ramp_adj ant_sw/trx_sw configuration and pa ramping up adjustment 0x09 pll_cp_adj pll charge pump current adjustment 0x0a if_freq_h if frequency setting (high byte) 0x0b if_freq_l if frequency setting (low byte) 0x0c if_freq_cca_h if frequency setting during cca operation (high byte) 0x0d if_freq_cca_l if frequency setting during cca operation (low byte) 0x0e bpf_adj_h bandpass filter bandwidth adjustment (high 2bits) 0x0f bpf_adj_l bandpass filter bandwidth adjustment (low byte) 0x10 bpf_cca_adj_h bandpass filter bandwidth adjustment during cca operation (high 2bits) 0x11 bpf_cca_adj_l bandpass filter bandwidth adjustment during cca operation (low byte) 0x12 rssi_lpf_adj rssi lowpass filter adjustment 0x13 pa_reg_fine_adj pa regulator fine adjustment 0x14 iq_mag_adj if i/q amplitude balance adjustment 0x15 iq_phase_adj if i/q phase balance adjustment 0x16 vco_cal_min_fl vco calibration low limit frequency setting (low byte)
fedl7396a/b/e-07 ml7396a/b/e 23/140 bank1 (continued) bit address symbol 7 6 5 4 3 2 1 0 description 0x17 vco_cal_min_fm vco calibration low limit frequency setting (middle byte) 0x18 vco_cal_min_fh vco calibration low limit frequency setting (high 4bits) 0x19 vco_cal_max_n vco calibration upper limit frequency setting 0x1a vco_cal_min vco calibration low limit value indication and setting 0x1b vco_cal_max vco calibration upper limit value indication and setting 0x1c vco_cal vco calibration value indication and setting 0x1d vco_cal_start vco calibration execution 0x1e bpf_adj_offset b pf adjustment offset value indication 0x1f-0x2a reserved reserved 0x2b # id_code id code indication 0x2c-0x32 reserved reserved 0x33 # pa_reg_adj1 pa regulator adjustment (1st setting) 0x34 # pa_reg_adj2 pa regulator adjustment (2nd setting) 0x35 # pa_reg_adj3 pa regulator adjustment (3rd setting) 0x36-0x39 reserved reserved 0x3a # pll_ctrl pll setting 0x3b-0x3e reserved reserved 0x3f # rx_on_adj2 rx_on timing adjustment #2 0x40-0x48 reserved reserved 0x49 # lna_gain_adj_m lna gain adjustment during middle gain operation 0x4a # lna_gain_adj_l lna gain adjustment during low gain operation 0x4b-0x4c reserved reserved 0x4d # mix_gain_adj_h mixer gain adjustment during high gain operation 0x4e # mix_gain_adj_m mixer gain adjustment during middle gain operation 0x4f # mix_gain_adj_l mixer gain adjustment during low gain operation 0x50-0x54 reserved reserved 0x55 #tx_off_adj1 tx_off ramping down adjustment 0x56-0x59 reserved reserved 0x5a # rssi_slope_adj rssi slope adjustment 0x5b-0x7f reserved reserved
fedl7396a/b/e-07 ml7396a/b/e 24/140 bank2 bit address symbol 7 6 5 4 3 2 1 0 description 0x00 bank_sel register access bank selection 0x01-0x11 reserved reserved 0x12 # sync_mode bit synchronization mode setting 0x13-0x1d reserved reserved 0x1e # pa_on_adj pa_on timing adjustment 0x1f # data_in_adj data enable timing adjustment 0x20-0x21 reserved reserved 0x22 # rx_on_adj rx_on timing adjustment 0x23 reserved reserved 0x24 # rxd_adj rxd timing adjustment 0x25-0x29 reserved reserved 0x2a rate_adj1 demodulator adjustment for optional data rate (low byte) 0x2b rate_adj2 demodulator adjustment for optional data rate (high 2 bits) 0x2c #ramp_cntrl ramp control enable setting 0x2d-0x5f reserved reserved 0x60 addfilcntrl address filtering function setting 0x61 panid_l panid setting for address filtering function (low byte) 0x62 panid_h panid setting for address filtering function (high byte) 0x63 64addr1 64bit address setting for address filtering function (1 st byte) 0x64 64addr2 64bit address setting for address filtering function (2 nd byte) 0x65 64addr3 64bit address setting for address filtering function (3 rd byte) 0x66 64addr4 64bit address setting for address filtering function (4 th byte) 0x67 64addr5 64bit address setting for address filtering function (5 th byte) 0x68 64addr6 64bit address setting for address filtering function (6 th byte) 0x69 64addr7 64bit address setting for address filtering function (7 th byte) 0x6a 64addr8 64bit address setting for address filtering function (8 th byte) 0x6b sht_addr0_l short address #0 setting for address filtering function (low byte) 0x6c sht_addr0_h short address #0 setting for address filtering function (high byte) 0x6d sht_addr1_l short address #1 setting for address filtering function (low byte) 0x6e sht_addr1_h short address #1 setting for address filtering function (high byte) 0x6f discard_count_l discarded packet number indication by address filtering (low byte) 0x70 discard_count_h discarded packet number indication by address filtering (high byte) 0x71-0x7f reserved reserved
fedl7396a/b/e-07 ml7396a/b/e 25/140 state diagram tx_on pllwait rx_on receive rx_on trx_off force_trx_off sleep tx_on a uto_ack_en tx_on rx_on start vco_cal trx_off force_trx_off vco_cal completion sleep trx_off idle sleep power off tx_on rx_on vco_cal sleep exit sleep exit sleep sleep trx_off force_trx_off sleep tx_on rx completed (trx_off) start rx (sfd detection) force_trx_off sleep trx_off force_trx_off sleep trasmit trx_off force_trx_off sleep rx on tx complete (trx_off) tx start force_trx_off sleep trx_off force_trx_off sleep rx_on vco_cal completion tx_on stop tx/ start rx start vco_cal trx_off force_trx_off sleep vcocal normal sequence (state transition) control from upper laye r ml7396 self controlled state transition state transition instruction ] p o w n [state slee /power off :sleep trx_ ff/idle :idle (tx-rx stand-by) pll_ ait :pll stand-by tx_on :tx ready (tx data waiting) transmit :tx on-going rx_o :rx readt (rx data waiting) receive :rx in process vco_cal :vco calibration on going
fedl7396a/b/e-07 ml7396a/b/e 26/140 functional description spi ml7396 family has a serial peripheral interface (spi), which supports slave mode. host mcu can read/write to the ml7396 registers and on-chip fif using mcu clock. single access mode and burst access mode are also supported. [single access mode] in write operation, data will be stored into internal register at rising edge of clock which is capturing d0 data. during write operation, if setting scen line to ?h?, the data will not be sotred into register. scen sdi sclk write data field address field w scen sdi sclk address field r sdo read data field [write] [read] a 6 a 0 a 6 a 0 d 7 d 0 d 7 d 0 ?1? ?0? [note] when using ieee802.15.4d mode, it is need to read ?length+1? bytes of data from rx fifo for switching the fifo banks correctly. after reading lngth bytes of data, need to access [r d_rx_fifo:b0 0x7f] register once more. (the last byte is invalid data.)
fedl7396a/b/e-07 ml7396a/b/e 27/140 [burst access mode] by maintaining scen as l, burst access mode will be active. by setting scen line to ?h?, exiting from the burst access mode. during burst access mode, address will be automatically incremented. when scen become h before clock for d0 is input, data transaction will be aborted. [note] if destination is [wr_tx_fifo:b0 0x7e] or [rd_rx_fifo: b0 0x7f] register, address will not be incremented. and continuous fifo access is possible. read data field scen sdi write data field address field w scen sdi sclk address field r sdo write data field read data field [write] [read] a 6 a 0 a 6 a 0 d 7 d 0 d 7 d 0 sclk ?1? ?0? [note] when using ieee802.15.4d mode, it is need to read ?length+1? bytes of data from rx fifo for switching the fifo banks correctly. (the last byte is invalid data.) afc function ml7396 family supports afc function during rx operation. frequency deviation (max +/- 20ppm) between remote device and local device can be compensated by this function. using this function, stable rx sensitivity and interference blocking performance can be achieved. this function can be activated by setting afc_en ([afc_cntrl:b0 0x34(0)]) =0b1 this is not supported for optional data rate. (other than 50/100/150/200/400kbps) when using optional data rate, afc_en should be set to 0b0.
fedl7396a/b/e-07 ml7396a/b/e 28/140 fifo ml7396 family has on-chio two 256byte fifos as tx -rx buffer. however, one fifo can store only one packet. (one packet cannot use two fifos). during rx, rx data is stored in a fifo (byte by byte), and the host mcu wil read rx data through spi. duting tx, the host mcu write tx data to a fifo (byte by byte) through spi and tenasmitting through rf. followings show the data format stored in fifo. as described below, input data format will be differe nt according to the setting va lue to ieee_mode ([packet mode_set:b0 0x45(1)]). (regardless of ieee_mode, prea mble and sfd bits are not stored into fifos) [ieee802.15.4g mode] (ieee_mode =0b1) [note; length, crc and ed value will be stored into data strage area other than fifo.] [ieee802.15.4d mode] (ieee_mode =0b0) length psdu (crc) 2byte 2/4byte [fec/crc_set] b0 0x46 2045/2043byte lsb msb (ed) 1byte [packet_mode_set] b0 0x45 (user data) length (crc) 1byte 128byte 125byte lsb msb (ed) 1byte [packet_mode_set] b0 0x45 length (max: 127byte) 2byte psdu (user data) data area stored into a fifo data area stored into a fifo length (max: 2047byte) [note; length, crc and ed value will be stored into data strage area other than fifo.] writeing or reading fifo will be done through spi with burst access. tx data is written to [wr_tx_fifo:b0 0x7e] register, and rx data is read from [rd_rx_f ifo:b0 0x7f] register. continuous access increments internal fifo address automatically. if burst access is suspended during write or read operation, address will be kept until the packet will beagain. two fifos (bank0, bank1) will be accessed one by another. if the host mcu writes tx data to a fifo during rx, rx fifo will use only single fifo. control of switching fifo banks will be done automatically. fifo status can be checked by [pd_data_req:b0 0x28] or [pd_data_ind:b0 0x29] register. [note] 1. when using ieee802.15.4d mode, it is need to read ?length+1? bytes of data from rx fifo for switching the fifo banks correctly. (the last byte is invalid data.) 2. in both tx and rx, length indicates psdu length includin g crc field. (not including ed fieled if selected) however during tx, the host mcu writes psdu excluding crc field to a fifo. during rx, the host mcu should read lngth field, user data field and crc fieled from a fifo.
fedl7396a/b/e-07 ml7396a/b/e 29/140 c tx fifo usage notification function this function is to notice un-transmitted data in tx_fifo (f ifo usage) to the mcu using sintn (interrupt) pin (#10) and/or dmon pin (#17). if un-transmitted data in tx_fifo (fifo usage) exceeds the full level threshold set by [tx_alarm_lh:b0 0x35] register, sintn pin will become ?l? (fifo-full interrupt) and/or dmon pin will become ?h?. and if the tx_fifo usage is equal to or less than the empty threshold level set by [tx_alarm_hl:b0 0x36] register, sintn will become ?l? (fifo-empty interrupt) and/or dmon pin will become ?l?. if re-generating the fifo-full interrupr (int[05], group1), after clearing the interrupt, once the tx_fifo usage should be equal or less than the empty level. if re-generating the fifo-empty interrupt (int[04], group1), after clearing the interrupt, one the tx_fifo usage excceds the full level threshold. tx empty level (address=0x0f) tx full level (address=0x3e) 0x00 0xff dmon pin will be ?h? when written data exceeds tx full level. dmon pin will be ?l? when tx data usage is smaller than tx empty level. [tx fifo usage] time tx full level tx empty level dmon signal tx data amount tx_fifo usage transition sintn signal tx data amount 0x0f 0x3e [note] 1. at default setting, dmon pin is configured as clkout output. if using dmon pin as this function, clkout_en ([clk_set:b0 0x02(4)]) =0b0 and fifo_trg_en ([crc_ area/fifo_trg:b0 0x77(0)])=0b1 are required. 2. each threshold should set as [tx_alarm_lh:b0 0x35] (full level) > [tx_alarm_hl:b0 0x36] (empty level).
fedl7396a/b/e-07 ml7396a/b/e 30/140 c rx fifo usage notification function this function is to notice un-read data in rx_fifo (fifo usage) to the mcu using sintn (interrupt) pin (#10) and/or dmon pin (#17). if un-read data in rx_fifo (fifo usage) exceeds the full level threshold set by [rx_alarm_lh:b0 0x37] register, sintn pin will become ?l? (fifo-full interrupt) and/or dmon pin will become ?h?. and if the rx_fifo usage is equal to or less than the empty threshold level set by [rx_alarm_hl:b0 0x38] register, sintn will becom ?l? (fifo-empty interrupt) and/or dmon pin will become ?l?. if re-generating the fifo-full interrupr (int[05], group1), after clearing the interrupt, once the rx_fifo usage should be equal or less than the empty level. if re-generating the fifo-empty interrupt (int[04], group1), after clearing the interrupt, one the rx_fifo usage excceds the full level threshold. rx emptylevel (address=0x0f) rx full level (address=0x3e) 0x00 0xff dmon pin will be ?h? when rx data exceeds rx full level. dmon pin will be ?l? when un-read data amount is less than rx empty level. [rx fifo usage] time rx data amount rx full level rx empty level dmon signal rx data amount rx_fifo usage transition sintn signal 0x0f 0x3e [note] 1. at default setting, dmon pin is configured as clkout output. if using dmon pin as this function, clkout_en ([clk_set:b0 0x02(4)]) =0b0 and fifo_t rg_en ([crc_area/fifo_trg:b0 0x77(0)]) = 0b1 are required. 2. each threshold should set as [rx_alarm_lh:b0 0x37] (full level) > [rx_alarm_hl:b0 0x38] (empty level). 3. if reading a portion of rx data from a fifo before receivi ng rx completion interrupt (int[18]/int[19] group3), please keep the fifo remaining size indicated by [rd_fifo_last:b0 0x7c] should be more than 0x01. 4. this function is valid only when data receiving. after rx completion, fifo-empty interrupt (int[04] group1) is not generated.
fedl7396a/b/e-07 ml7396a/b/e 31/140 c fifo control method when using fifo address (1) tx condition: auto_tx ([packet_mode_set:b0 0x45(2)]) =0b1 and fifo access size is 128 czuft set [fast_tx_set;b0 0x6a] register and fifo_adr_en ([packet_mode_set:b0 0x45(7)]) =0b1. write256 bytesdata to fifo ([wr_tx_fifo:b0 0x7e] register) via spi interface. * when the amount of written data reaches [fifo_tx_set:b0 0x6a] register, transmission starts. read [rd_fifo_last:b0 0x7c] register. when fifo address indication (hereafter, read pointer) is 128 or more and the remaining tx data is 128 bytes or more, writing 128 bytes data to fifo. if remaining tx data is less than 128 bytes, go to . read [rd_fifo_last] register. when read pointer is 64 or less and the remaining tx data is 128 bytes or more, writing 128 bytes data to fifo. if remaining tx data is less than 128 bytes, go to . repeat and until for the necessary amount of tx data. writing whole remaining data to fifo and wait tx completion interrupt (int[16] / int[17], group3) notification. y es read pointer t 128? [rd_fifo_last:b0 0x7c] no y es remaining tx data t 128 bytes? write 128 bytes data to a fifo [wr_tx_fifo:b0 0x7e] y es 64 t read pointer? [rd_fifo_last:b0 0x7c] remaining tx data t 128 bytes? no no wait for tx completion int. [int_source_grp3:b0 0x26] write 256 bytes to a fifo [wr_tx_fifo:b0 0x7e] no y es time amount of transmitted data ( b y te ) total tx data [ transmit] start transmission tx fifo address indication 255 tx fifo address indication (read pointer) increments after tx start. after transimitting 256 th byte data, the address indication is turned to 0 and increments again. write 128 bytes data to a fifo [wr_tx_fifo:b0 0x7e] write remaining data to a fifo [wr_tx_fifo:b0 0x7e] if data amount written to a fifo exceeds the fast_tx_trg[7:0], tx will start.
fedl7396a/b/e-07 ml7396a/b/e 32/140 (2) rx (fifo access size is 128 bytes) set fifo_adr_en ([packet_mode_set:b0 0x45(7)]) =0b1, and issuing rx_on by [rf_status:b0 0x6c] register. (rx start) read [rd_fifo_last:b0 0x7c] register. when fifo address indication (hereafter, write pointer) is 5 or more, read 5 bytes from fifo ([rd_rx_fifo:b0 0x7f] register). at this time, if the length field is less than 5, this paclet does not meet ieee802.15.4 requirement of the minimum packet length, the the packet might be discarded. (* it is not applied when using an original packet format other than ieee802.15.4.) when it is equal to or more than 5 and less than 128, wait rx completion interrupt (int[18]/[19] group3) and then read out the remaining data from fifo. at , if the length field is 128 or more, after write pointer is 128 or more, read 123 bytes from fifo. after that, if the remaining rx data size is less than 128, go to . at , if the remaining rx data size is 128 or more, after write pointer is 0 to 127, read 128 bytes from fifo. after that, if the remaining rx data size is less than 128, go to . at , if the remaining rx data size is 128 or more, after write pointer is 128 to 255, read 128 bytes from fifo. after that, if the remaining rx data size is less than 128, go to . repeat and until for the necessary amount of rx data. after rx completion interrupt (int[18]/int[19], group3) notification, read out the remaining rx data from fifo. rx_on issue [rf_status:b0 0x6c] y es write pointer 5? no [rd_fifo_last:b0 0x7c] y es read 5 bytes from fifo and length 5? discard packet clear fifo [rst_set:b0 0x01] read remaining data [rd_rx_fifo:b0 0x7f] no y es rx completion? (int[18]/[19]) [ int_source_grp3:b0 0x26] write pointer 128? [rd_fifo_last:b0 0x7c] 0 write pointer 127? [rd_fifo_last:b0 0x7c] read 128 bytes [rd_rx_fifo:b0 0x7f] read 128 bytes [ rd rx fifo:b0 0x7f ] read 128 bytes [rd_rx_fifo:b0 0x7f] remainin g amoun t 128? remainin g amoun t 128? remainin g amoun t 128? no no no 128 write pointer 255? [rd_fifo_last:b0 0x7c] y es y es y es no no no y es y es y es no y es length 128? no time amount of received data (byte) total rx data [receive] rx fifo address indication (read pointer) increments after rx start. after receiving 256 th byte data, the address indication is turned to 0 and increments again. start receiving rx fifo address indication 255
fedl7396a/b/e-07 ml7396a/b/e 33/140 packet format ml7396 family supports following packet format. (in dio mode, the packet format is preamble, sfd+dio data) preamble and sfd field are automatically inserted in tx, and au tomatically detected and deleted in rx. the host mcu need not concern those packet handling. [ieee802.15.4g mode] (ieee_mode ([packet_mode_set:b0 0x45(1)]) =0b1) manchester coding field [note] 1. the following shows the bit assignment of length field (phr) in ieee802.15.4g format. it is different from ieee802.15.4d format. user dara fieled (after 3 rd byte) will be output with lsb first. 2. when using crc32, the minimum user data length is 4 bytes. when transmitting/receiving 3-bytes data, crc16 should be used. ack packet cannot be received under crc32 setting. fifo storage area 2/4byte [b0 0x46] [b0 0x42] [b0 0x39] [b0 0x3a?0x3d] [b0 0x3e?0x41] [b0 0x43] length psdu (crc) lsb msb preamble sfd tx: automatic insertion rx:auto detection/deletion 2byte 3 to 2045byte whitening field crc field (ed) (user data) 1byte [b0 0x45] 1 s t byte 2 n d byte input from spi reserv reserved mode fcs ed whiteni ng l4 l3 l2 switch length l10 l9 l1 l8 l7 l6 l0 l5 reserved output to air tx starting bit mode switch reserved fcs length whiteni ng l4 l3 l2 l1 l10 l9 l8 l7 l6 l0 l5 after 3rd byte l6 l4 l5 l1 l7 l3 l0 l2 l1 l3 l2 l6 l0 l4 l7 l5
fedl7396a/b/e-07 ml7396a/b/e 34/140 [ieee802.15.4d mode] (ieee_mode ([packet_mode_set:b0 0x45(1)]) =0b0) manchester coding field [note] #1 when in 802.15.4d mode, if setting crc_area ([crc_area/fifo_trg:b0 0x77(1)] bit (physet101 bit1) =0b1, crc calculationn area will be extended to length field (length+psdu). 1. the following shows the bit assignment of length field (phr) in ieee802.15.4d format. it is different from ieee802.15.4g format. user dara fieled (after 2 nd byte) will be output with lsb first. input from spi output to air l7 l6 l5 l4 l3 l2 l1 l0 l0 l1 l2 l3 l4 l5 l6 l7 tx starting bit 2byte [b0 0x46] [b0 0x42] [b0 0x39] [b0 0x3a?0x3d] [b0 0x3e?0x41] [b0 0x43] length psdu (crc) lsb msb preamble sfd tx : automatic insertion rx: auto detection/deletion 2byte 3 to 125byte whitening field crc field (#1) (ed) (user data) 1byte [b0 0x45]
fedl7396a/b/e-07 ml7396a/b/e 35/140 data whitening function ml7396 family supports data whitening function specified in ieee 802.15.4g standard. the following figure shows the pn9 pattern generator. the generated pattern will be ?xor? with data located in psdu area. initialization value can be configured by [pn9_set_l:b0 0x7a] and [pn9_set_h:b0 0x7b] registers. when setting pn9_en ([pn9_set_h:b0 0x7b(7)]) =0b1, this generator can be used as random number generator. when whitening ([packet_mode_set:b0 0x45(4)]) =0b1, whitening condition is set by ieee_mode ([packet_mode_set:b0 0x45(1)] setting. please refer to the "packet format". ? in ieee802.15.4d mode (ieee_mode=0b0), data whitening applied to every tx or rx packet ? in ieee802.15.4g mode (ieee_mode=0b1), data whitening will be applied to the packet which whitening bit in phr fieled is set to 0b1 [note] 1. the pn9 pattern generator shares setting with the whitening function. while the whitening function is running, pn9_en should be set to 0b0. tx: en = rn pn9n rx: rn = ren pn9n en: whitening bits as tx data rn: data bits ren: whitening bits as rx data pn9n: pn9 pattern (initialization value 0b111111111) fig. pn9 pattern generator fec function ml7396 family supports fec function. fec function will be applied to phr and psdu field as shown in below. [note] 1. length in phr fieled should be set the length before fec encoding. 2. when using whitening function at same time, whitening will apply to the fec encoded data. for more details of whitening field, please refer to the ?packet format?. 3. inrerleaving mode is not compliant to ieee802.15.4g. d d d d d d d d d pn9 phr msb lsb psdu (crc) preamble sfd (user data) fec field
fedl7396a/b/e-07 ml7396a/b/e 36/140 energy detection value (ed value) function ml7396 family supports calculating energy detection value (her e in after ed value) based on received signal strength indicator (rssi). ed value acquisition can be enabled by ed_calc_en ([ed_cntrl:b0 0x1b(7)])=0b1, and as soon as transition to rx_on state. and acquired ed value will be indicate at [ed_rslt:b0 0x16] register. when ed_calc_en=1, ed value will be updated constantly during rx_on state. even if ed_calc_en=1, while cca operation or diversity search operation, ed value will not be updated. after completion of cca operation, diversity search, ed value will be updated. ed value is not rssi value at given timing, but average values. the number of average times can be specified by register ed_avg[2:0] ([ed_cntrl:b0 0x1b(2-0)]). during divers ity operation, 2div_ed_avg[2:0] ([2div_ed_avg:b0 0x6d(2-0)]) is used for setting. after acquiring specified av erage ed value, ed_done [ed_cntrl:b0 0x1b(4)] becomes ?0b1?, and [ed_rslt:b0 0x16] register is updated. ed_done bit will be cleared if one of the following conditions is met. 1. gain is switched. 2. suspend ed value acquisition and then resume it. 3. antenna is switched. (when diversity is enabled) timing from ed value starting point ot ed value acquisition is calculated as following formula. ed value averaging time = ad conversion time (17.7 s/16 s) * number of average times note; ad conversion time can be set by adc_clk_set ([adc_clk_set:b0 0x08(4)]) default value is 1.8mhz and sdc conversion time is 17.7 s [timechart] [condition] set adc_clk_set([adc_clk_set: b1 0x08(4)])=0b1 (2mhz) set ed_avg[2:0] ([ed_ctrl: b0 0x1b(2-0)])=0b011 (8 times averaging) ed value calculation execution flag rssi value (internal signal) ad conversion (17.8/16usec) [adc_clk_set:b0 0x08(4)] ed_done ([ed_cntrl:b0 0x1b(4)]) (internal signal) rssi 6 rssi 7 rssi 8 rssi 9 rssi 1 rssi 2 rssi 3 rssi 4 rssi 5 ed_value [ed_rslt:b0 0x16] ed value averaging period ( 16 s*8=128 s) ed_avg[2:0] ([ed_cntrl: b0 0x1b(2-0)]) 2div_ed_avg[2:0] ([2div_ed_avg:b0 0x6d (2-0)]) compensation and averaging ed ed ed invalid 3-10 2-9 1-8 constantly update by moving averaging
fedl7396a/b/e-07 ml7396a/b/e 37/140 c ed value calculation input level and ed value are descrived in the following formula. during cca operation, ed value is bigger than normal case, since the bpf setting is modified. therefore, cca comp ensation value should be attached to the normal case. input level is defined at antenna connector in the ciruit described in the ?application circuit example?. and antenna sw loss is assumed 0.5db. [ 200kbps] ed value = 255/70 * (107 + input level [dbm] - variation - other loss) + cca cpmpensation [400kbps] ed value = 255/62 * (99 + input level [dbm] - variation - other loss) parameter value variations (individual, temp.) 6db other loss antenna, matching circuit loss cca compensation 12@100kbps, 16@200kbps, 0@other rates
fedl7396a/b/e-07 ml7396a/b/e 38/140 diversity function ml7396 family supports two antenna diversity function. while setting 2div_en ([2div_cntrl: b0 0x71(0)])=0b1, as s oon as rx_on is set, diversity mode will start. when diversity mode is started, and upon rx data detection, each ed value will be acquired by switching two antennas. and then antenna with higher ed value will be selected automatically. as diversity uses preamble data for ed value acquisition, longer preamble length is desirable. if preamble is t oo short, accurate ed values may not be obtained. the timing example is as below. rx packet preamble length data sfd ed values and antenna diversity result will be cleared when as below: 1. diversity search completion interrupt (int[09] group2) is cleard. 2. fifo* rx competion interrupt (int[18] or int[19] group3) is cleared 3. diversity resume by errounous detection ed values and diversity result should be read before clearing diversity search completion or fifo* rx completion interrupt. during receiving state, clearing diversity search completion interrupt causes the data error since diversity operation wlll resume by the interrupt clearance. diverstiy search completion interrupt should be cleared at same timing of fifo* rx completion interrupt clearance. ml7396 supports recovering function from incorrect diversity completion caused by errornous detection due to thermal noize, after dicersity search completion, if preamble can not be detected until antenna search timer expiration, ml7396 judges the previous diversity search comple tion is incorrect and resume diversity operation automatically. when resume diversity operation for next packet receiving, please clear rx completion interrupt and diversity search completion interrupt. (note) 1. when an incorrect diversity completion caused by errornous detection due to thermal noize, ml7396 resume antenna diversity automatically. but when receiving a desired signal during the process of errounous detection, ed value obtained by [ant1_ed:b0 0x73] or [ant2_ed:b0 0x74] may indicate a low value different from the actual input level. if this event occures, the actual ed value of desired signal can be achibed by reading [ed_rslt:b0 0x16] registers after sfd detection interrupt (int[11] group2) generation. 2. when rf state is changed to tx_on state immediately after an incorrect diversity completion caused by errornous detection, ml7396 judges diversity search is done. then, diversity search is not operated at next receiving. in this case, please clear diversity search completion interrupt (int[09] group2) by next receiving. rf state antenna ant1 ed search period antenna selection search_time[6:0] ([2div_search: b0 0x6f(6-0)]) trx_off rx_on receive ant1/ant2 search is repeated int[09] (diversity search completion) [int_source_grp2: b0 0x25] ant1/2 ant2 antenna with higher ed ant1 ant2 ed stabilization search period period rssi_stable[3:0] ([rssi_stable_time: b0 0x22(3-0)])
fedl7396a/b/e-07 ml7396a/b/e 39/140 c antenna switching function by using [2div_ctrl: b0 0x71], [rf_ctrl_set: b0 0x75] registers, ml7396 can support both spdt and dpdt antena swith control. ant_sw pin (#20) and trx_sw pin ( #21) output considion for each antenna switch are explained below. dpdt switch set 2port_sw([2div_ctrl:b0 0x71(1)])=0b1, ant_ctrl1([2div_ctrl: b0 0x71(5)])=0b0. ant_sw, trx_sw output condition of each idle, tx, rx state are as follow. (default setting) if inv_trx_sw([2div_ctrl:b0 0x71(2)])=0b1, polarity of ant_sw pin (#20) and trx_sw pin (#21) are reversed. inv_trx_sw=0b0 (default setting) inv_trx_sw=0b1 (reversed polarity) tx/rx state ant_sw trx_sw ant_sw trx_sw description idle h l l h idle state tx l h h l tx state h l l h when diversity disable or initial condition when diversity enable is set ([2div_ctrl: b0 0x71(0)]=0b1). rx l/h h/l h/l l/h if diversity enable is set, during searching, (ant_sw=h, trx_sw=l) and (ant_sw=l, trx_sw=h) are switched alternatively. after diversity completion, fix to one of the condition. spdt switch set 2port_sw([2div_ctrl:b0 0x71(1)])=0b0, ant_ctrl1([2div_ctrl: b0 0x71(5)])=0b0. ant_sw, trx_sw output condition of each idle, tx, rx state are as follow. (default setting) if inv_trx_ sw([2div_ctrl: b0 0x71(2)])=0b1, polarity of trx_sw pin (#21) is reversed. inv_trx_sw=0b0 (default setting) inv_trx_sw=0b1 (polarity reverse) tx/rx condition ant_sw trx_sw ant_sw trx_sw description idle l l l h idel state tx l h l l tx state l l l h when diversity disable or initial condition when diversity enable is set ([2div_ctrl: b0 0x71(0)]=0b1). rx h/l l h/l h if diversity enable is set,during searching (trx_sw=h) and (trx_sw=l) is switched alternatively. after diversity completion , fix to one of the condition.
fedl7396a/b/e-07 ml7396a/b/e 40/140 in the above setting, if inv_ant_sw([2div_ctrl: b0 0x71(3)])=0b1, ant_ctrl1([2div_ctrl: b0 0x71(5)])=0b1 are set, polarity of ant_sw pin (#20)is reversed. inv_ant_sw=0b0 ant_ctrl1=any (default setting) inv_ant_sw=0b1 ant_ctrl1=0b1 tx/rx state ant_sw trx_sw ant_sw trx_sw description idle l l h l idle state tx l h h h tx state l l h l when diversity disable or intial codition when diversity enable is set ([2div_ctrl: b0 0x71(0)]=0b1). rx h/l l l/h l if diversity enable is set, during searching (ant_sw=h) and (ant_sw=l) is switched alternatively. after diversity completion, fix to one of the condition. c antenna switch forced setting ant_sw pin (#20) and trx_sw pin (#21) output conditions can be set to fix by [rf_cntrl_set: b0 0x75] register, or 2div_rslt2 ([2div_rslt:b0 0x72(1)]) and inv_trx_sw ([2div_cntrl:b0 0x71(2)]) when diversity fuction is diabled. 1. forced setting by [rf_cntrl_set] register ant_sw pin: by ant_sw_en (bit1)=0b1, ant_sw_set (bit5) condition will be output. trx_sw pin: by trx_sw_en (bit0)=0b1, trx_sw_set (bit4) condition will be output. 2. forced setting by 2div_rslt2 bit and inv_trx_sw bit when diversity function is disabled ( 2div_en ([2div_cntrl:b0 0x71(0)])=0b0) ant_sw pin: when 2div_rslt2=0b0, output ?l?. when 0b1, output ?h?. trx_sw pin: when inv_trx_sw=0b0, output ?l?. when 0b1, output ?h?. output defined by [rf_cntrl_set:b0 0x75] registers setting has higer priority. when diversity is enable (2div_en=0b1), output definced by 2div_rslt2 and inv_trx_sw are ignored. any antenna switch setting is inhibited to avoid out-of-synchronization during receive state.
fedl7396a/b/e-07 ml7396a/b/e 41/140 antenna switching control signals can be also used as below. example 1) using one dpdt switch please set 2port_sw([2div_ctrl: b0 0x71(1)])=0b1. ml7396a_b_e (note) altenate external pa control signal exists (dcnt pin). (note) external circuits around lna_p pin, pa_out pin and antenna switch (dpdt#1) are omitted in this example. example 2) using 2 spdt switches please set 2port_sw([2div_ctrl: b0 0x71(1)])=0b0. (note) altenate external pa control signal exsits. (dcnt pin) (note) external circuits around lna_p pin, pa_outpin and antenna switch(spdt#2) are omitted in this example. dpdt#1 lna_p pin (#30) pa_out pin (#27) trx_sw pin (#20) ant_sw pin (#21) dcnt pin (#22) ml7396a_b_e spdt#2 spdt#1 lna_p pin (#30) pa_out pin (#27) trx_sw pin (#20) ant_sw pin (#21) dcnt pin (#22)
fedl7396a/b/e-07 ml7396a/b/e 42/140 cca (clear channel assessment) function ml7396 family has cca function that will check availability of certain channel. 3 type of modes are available, normal mode, continuous mode, idle detection mode. [cca mode setting] at normal operation [cca_cntrl:b0 0x15] cca mode bit4 (cca_en) bit3 (cca_idle_en) bit5 (cca_loop_start) normal mode 0b1 0b0 0b0 continuous mode 0b1 0b0 0b1 idle detection mode 0b1 0b1 0b0 when using auto_ack [auto_ack_set:b0 0x55] [cca_cntrl:b0 0x15] cca mode bit4 (auto_ack_en) bit7 (cca_auto_en) idle detection mode 0b1 0b1 when using address filtering [addfil_cntrl:b2 0x60] [packet_mode_set:b0 0x45] cca mode bit0 to bit4 bit0 (addfil_idle_det) idle detection mode set 0b1 to any bits 0b1
fedl7396a/b/e-07 ml7396a/b/e 43/140 c normal mode normal mode determines idle or busy. cca (normal mode) will be executed when rx_on is issued while cca_en ([cca_cntrl:b0 0x15(4)])=0b1, cca_idle_en ([cca_cntrl:b0 0x15(3)])=0b0 and cca_loop_start ([cca_cntrl:b0 0x15(5)])=0b0 are set. the judgement of cca is determined by average ed value in [ed_rslt:b0 0x16] and threshold value defined by [cca_level:b0 0x13] register. if average ed value exceeds cca threshold value, it is determined as ?busy?. and set cca_rslt[1:0] ([cca_cntrl:b0 0x15(1-0)]) =0b01 is set. if ed value is smaller than cca threshold, and maintains idle detection period which is defined by idle_wait[9:0] of the [idle_wait_l:b0 0x17], [idle_wait_h:b0 0x18] resisters, it is determined as ?idle?. and cca_rslt[1:0] = 0b00 is set. for details operation of idle_wait[9:0], please refer to ?idle detection for long period?. if ?busy? or ?idle? is determined, cca_done [cca_cntrl:b0 0x15(2)] will become 0b1 and cca completion interrupt (int[08] group2) is generated. cca_en bit will be cleared to 0b0 automatically. when cca completion interrupt is cleared, cca_rslt[1:0] are reset to 0b00. therefore cca_rslt[1:0] need to be read before clearing cca completion interrupt. if an ed value exceeds the value defined by [cca_ignore_level:b0 0x12] register, and as long as a given ed value is included in the averaging target of ed value calculation, idle judgment is not performed. in this case, if average ed value exceeds cca threshold value, it is determined as ?busy? and cca operation is terminated. however, if average ed value is smaller than cca threshold value, idle judgment is not determined. and cca_rslt[1:0] indicates 0b11. cca operation continues until ?busy? is ditermined or the given ed value is out of the averaging target and ?idle? is determined. for detail operation of ed value exceeding [cca_ignore_level:b0 0x12] register, please refer to "idle determination exclusion under strong signal input". timing from cca command issue to the cca completion is calculated as the following formula. [idle detection] cca execution time = (ed value average times + idle_wait setting) * a/d conversion time + filter stabilization time (a/d conversion time* 2) [busy detection] cca execution time = ed value average times * a/d conversi on time+ filter stabilization time (a/d conversion time* 2) [note] 1. above formula does not consider idle judgment exclusion based on [cca_ignore_level:b0 0x12] register. for details, please refer to "dle determination exclusion under strong signal input ". 2. a/d conversion time can be selected by adc_clk_set ([adc_clk_set:b0 0x08(4)]). adc_clk_set=0b0: 17.8 s, 0b1: 16 s
fedl7396a/b/e-07 ml7396a/b/e 44/140 the following is timing chart for normal mode. [conditions] adc_ck_set ([adc_clk_set:b0 0x08(4)])=0b1 (2mhz) ed_avg[2:0] ([ed_cntrl:b0 0x1b(2-0)])=0b011 (ed value 8 times average) idle_wait[9:0] ([idle_wait_l/h:b0 0x17/0x18(1-0)])=0b00_0000_0000 (idle detection 0 s) [idle detection case] cca_en [busy detection case] [note] 1. after issuing cca command, transit into no-input state, and exit this state after filter stbilization. 2. when the iput level chnge from no-input to -80dbm, it takes around 32 s for indicating -80dbm ed value. ed value (internal signal) cca_rslt[1:0] [cca_cntrl:b0 0x15(1-0)] cca_done [cca_cntrl:b0 0x15(2)] [cca_cntrl:b0 0x15(4)] ed value[7:0] [ed_rslt:b0 0x16] ad conversion (16 s) ed value average period (16 s * 8=128 s) 0b10 (cca on-going) ed1 ed3 ed5 ed2 ed6 ed7 filter stabilization 16 to 32 s ed0 averaging ed ( 0-7 ) < cca_th_lv b0 0x13 0b00 (idle) idle_wiat[9:0] should be set, for idle detection for longer period cca execution time (max. 32 s+128 s=160 s) cca_en ed value (internal signal) cca_rslt[1:0] [cca_cntrl:b0 0x15(1-0)] cca_done [cca_cntrl:b0 0x15(2)] [cca_cntrl:b0 0x15(4)] ed value[7:0] [ed_rslt:b0 0x16] ad conversion (16 s) ed value averaging (16 s * 8=128 s) 0b10 (cca on-going) ed1 ed3 ed5 ed2 ed6 ed7 filter stabilization 16 to 32 s ed0 averaging ed (0-7) > cca_th_lv b0 0x13 0b01 (busy) idle_wiat[9:0] should be set, for idle detection for longer period cca execution time (max. 32 s+128 s=160 s)
fedl7396a/b/e-07 ml7396a/b/e 45/140 c continuous mode continuous mode continues cca operation until terminated by the host mcu. cca continuous mode will be executed when rx_on is issued while cca_en ([cca_cntrl:b0 0x15(4)])=0b1, cca_idle_en ([cca_cntrl:b0 0x15(3)])=0b0 and cca_loop_start ([cca_cntrl:b0 0x15(5)])=0b1 are set. like normal mode, cca is determined by average ed value in [ed_rslt:b0 0x16] register and threshold value defined by [cca_level:b0 0x13] register. if average ed value exceeds cca threshold, it is determined as ?busy?, set cca_rslt[1:0] ([cca_cntrl:b0 0x15(1-0)]) =0b01. if ed value is smaller than cca threshold, and maintains idle detection period which is defined by idle_wait[9:0] of the [idle_wait_l:b0 0x17], [idle_wait_h:b0 0x18] resisters, it is determined as ?idle?. and cca_rslt[1:0] = 0b00 is set. for details operation of idle_wait[9:0], please refer to ?idle detection for long period?. if an ed value exceeds the value defined by [cca_ignore_level:b0 0x12] register, and as long as a given ed value is included in the averaging target of ed value calculation, idle judgment is not performed. in this case, if average ed value exceeds cca threshold value, it is determined as ?busy? and cca operation is terminated. however, if average ed value is smaller than cca threshold value, idle judgment is not determined. and cca_rslt[1:0] indicates 0b11. for detail operation of ed value exceeding [cca_ignore_level:b0 0x12] register, please refer to "idle determination exclusion under strong signal input". continuous mode does not stop when ?busy? or ?idle? is determined. cca operation continues until 0b1 is set to cca_loop_stop ([cca_cntrl:b0 0x15(6)]). result is updated every time ed value is acquired. cca_done ([cca_cntrl:b0 0x15(2)]) will not be 0b1, and cca completion interrupt (int[08] group2) will not be generated.
fedl7396a/b/e-07 ml7396a/b/e 46/140 the following is timing chart for continuous mode. [conditions] adc_ck_set ([adc_clk_set:b0 0x08(4)])=0b1 (2mhz) ed_avg[2:0] ([ed_cntrl:b0 0x1b(2-0)])=0b011 (ed value 8 times average) idle_wait[9:0] ([idle_wait_l/h:b0 0x17/0x18(1-0)])=0b00_0000_0000 (idle detection 0 s) [bust to idle transitions, terminated with cca_loop_stop] after cca_loop_stop is issued, cca_loop_start, cca_en and cca_loop_stop are automatically cleared. [note] 1. after issuing cca command, transit into no-input state, and exit this state after filter stbilization. 2. when the iput level chnge from no-input to -80dbm, it takes around 32 s for indicating -80dbm ed value. ed (21-28) ed (43-50) ed value (internal signal) ad conversion (16 s) ed value average period (128 s) 0b10 (cca on-going) ed0 ed7 ed8 ed28 cca_loop_start/ cca_en [cca_cntrl:b0 0x15(5,4)] 0b00 (idle) ed value[7:0] [ed_rslt:b0 0x16] invalid averaging > cca_th_lv b0 0x13 ed (0-7) fedl7396a/b/e-07 ml7396a/b/e 47/140 c idle detection mode idle detection mode continues cca until idle detection. idle detection cca will be executed when rx_on is issued while cca_en ([cca_cntrl:b0 0x15(4)])=0b1, cca_idle_en ([cca_cntrl:b0 0x15(3)])=0b1 and cca_loop_start ([cca_cntrl:b0 0x15(5)])=0b0 are set. when auto_ack function is enabled by auto_ack_en ([auto_ack_set:b0 0x55(4)])=0b1, if cca_auto_en ([cca_ctrl:b0 0x15(7)]) =0b1, cca idle detection mode is performed before transsmitting ack packet. and when address filtering function is enable by setting 0b1 to any bit0 to bit4 of [addfil_cntrl:b2 0x60] register, if addfil_idle_det ([packet_mode_set:b0 0x45(0)])=0b1, cca idle detection mode is performed after address mismatch detection. like normal mode, cca is determined by average ed value in [ed_rslt:b0 0x16] register and threshold value defined by [cca_level:b0 0x13] register. if average ed value exceeds cca threshold, it is determined as ?busy?, set cca_rslt[1:0] ([cca_cntrl:b0 0x15(1-0)]) =0b01. if ed value is smaller than cca threshold, and maintains idle detection period which is defined by idle_wait[9:0] of the [idle_wait_l:b0 0x17], [idle_wait_h:b0 0x18] resisters, it is determined as ?idle?. and cca_rslt[1:0] = 0b00 is set. for details operation of idle_wait[9:0], please refer to ?idle detection for long period?. in idle detection mode, only when idle is detected, cca_done ([cca_cntrl:b0 0x15(2)]) wil be set to 0b1 and cca completion interrupt (int[08] group2) is generated. if cca operation is performed by cca_en=0b1, after idle detection, cca_en and cca_idle_en are reset to 0b0. upon clearing cca completion interrupt, cca_rslt[1:0] are reset to 0b00. cca_rslt[1:0] should be read before clearing cca completion interrupt. if an ed value exceeds the value defined by [cca_ignore_level:b0 0x12] register, and as long as a given ed value is included in the averaging target of ed value calculation, idle judgment is not performed. in this case, if average ed value is smaller than cca threshold value, idle judgment is not determined. and cca_rslt[1:0] indicates 0b11. cca operation continues until given ed value is out of averaging target and ?idle? is determined. for details of ed value exceeding [cca_ignore_level: b0 0x12] register, please refer to ?idle determination exclusion under strong signal input?.
fedl7396a/b/e-07 ml7396a/b/e 48/140 the follwing is timing chart for idle detection. [upon busy detection, continue cca and idle detection case] [conditions] adc_ck_set ([adc_clk_set:b0 0x08(4)])=0b1 (2mhz) ed_avg[2:0] ([ed_cntrl:b0 0x1b(2-0)])=0b011 (ed value 8 times average) idle_wait[9:0] ([idle_wait_l/h:b0 0x17/0x18(1-0)])=0b00_0000_0000 (idle detection 0 s) after idle detection, cca will be completed, then cca_en, cca_idle_en are reset to 0b0 automatically.. cca_en/cca_idle_en [note] 1. after issuing cca command, transit into no-input state, and exit this state after filter stbilization. 2. when the iput level chnge from no-input to -80dbm, it takes around 32 s for indicating -80dbm ed value. ed (21-28) ed (22-29) ed value average period 0b10 (cca on-going) ed0 ed7 ed8 ed28 [cca_ctrl: b0 0x15(4-3)] ad conversion (16 s) filter stabilization 16 to 32 s idle detection period 0b00 (idle) invalid ed value ed27 ed29 (internal signal) averaging ed_value[7:0] ed ed ed cca execution period (min.128 s+idle detection period) (20-27) [ed_rslt: b0 0x16] (0-7) (1-8) cca_th_lv b0 0x13 b0 0x13 cca_rslt[1:0] [cca_cntrl: b0 0x15(1-0)] 0b01 (busy) if busy, interrupt not generated cca_done [cca_cntrl: b0 0x15(2)] idle_wait[9:0] should be set, for idle detection for longer period.
fedl7396a/b/e-07 ml7396a/b/e 49/140 c idle determination exclusion under strong signal input if acquired ed value exceeds [cca_ignore_lvl: b0 0x12] register, idle dertermination is not performed as lon as a given ed value is included in the averaging target range. if average ed value including this strong ed value indicated in [ed_rslt: b0 0x16] register exceeds the cca threshold value defined by [cca_level: b0 0x13] register, it is considered as ?busy?. and cca_rslt[1:0]([cca_ctrl: b0 0x15(1-0)])=0b01 is set. if average ed value is smaller than cca threshold value, idle determination is not performed and cca_rslt[1:0] indicates 0b11 ?cca evaluation on-going (ed value excluding cca judgement acquisition)?. cca will continue until ?idle? or ?busy? determination (in case of idle detection mode, ?idle2 is determined. in case of continuous mode, cca_loop_stop([cca_ctrl: b0 0x15(6)]) is issued.) [note] cca completion interrupt (int[08] group2) is generated only when ?idle? or ?busy? is determined. therefore, if data whose ed value exceeds ignore_lv[7:0] ([cca_ignore_level:b0 0x12(7-0)]) are input intermittently, neither ?idle? or ?busy? can be determined and cca may continues. [ed value acquisition under extrem strong signal] ed value >cca_ignore_lvl e ( d value analog) ignore_lv[7:0] [cca_ignore_level: b0 0x12] ed value sh if t regi st er (ed val ue 8 t im es average) [ti me 1] [t im e2] [ti me 3] [ti me 8] [ti me 9] av eraging ta rget incl udes ed va lue exceedi ng igno re_lv[7:0]. in t his case, ?idl e? is not deter mined. ho we ve r, if averagi ng va lue exceeds c ca thre shold, ?bus y? is de term ined. tim e ed v alue, wh ich in cludes ign or e_l v[7:0], is out of av eraging t arge t. in thi s case , ?idl e? can be determ ine d.
fedl7396a/b/e-07 ml7396a/b/e 50/140 the follwing is timing chart for cca determination exclusion under strong signal. [during idle_wait counting, detected extremly strong signal. after the given signal is out of averaging target, idle detection case] [condition] cca normal mode adc_ck_sel ([adc_clk_set: b0 0x08(4)])=0b1 (2mhz) ed_avg[2:0] ([ed_ctrl: b0 0x1b(2-0)])=0b011 (ed value 8 times average) idle_wait[9:0] ([idle_wait_l/h: b0 0x17/18( 1-0)])=0b00_0000_0111(idle detection period 112 s) ed value>cca_ignore_level [note] 1. after issuing cca command, transit into no-input state, and exit this state after filter stbilization. 2. when the iput level chnge from no-input to -80dbm, it takes around 32 s for indicating -80dbm ed value. ed7 inv al id ed (0-7) ed (1-8) ed (6-13) ed8 ed1 3 ed1 4 0x0 01 0x0 06 0b11 (on-goi ng) 0x0 00 ed (14-21) ed (7-14) ed value>cca _ig nore _lev el detec ti on and res et due to ext reme strong si gnal de te ct io n, cca_ rsl t i s not indi ca ti ng id le. cca_ rsl t[ 1: 0]= 0b11 do not generat e in te rrupt ed1 5 ed (8-15) ed2 1 ed (22-29) ed2 2 ed (15-22) 0x0 07 ed2 9 0b00 (idle ) resu me c ounti ng due t o t he ex tr em e st rong s ignal is out of averaging ta rget. cc a _ rsl t ma int ain s u nt il id le/ bus y de te cted. ed valuecca _ th _ ll , t hen b us y det ec ti on. ) ed_v alue[7:0] [e d_rsl t: b0 0x16] cc a_pr og [9:0] [c ca_p rog_l/ h:b 0 0x 19/1a ] cc a_r slt [1:0] 0b10 (on-going) [c ca_cntrl: b0 0x 15(1-0)] cca_d one [c ca_cntrl: b0 0x 15(2)]
fedl7396a/b/e-07 ml7396a/b/e 51/140 c idle detection for long period when cca idle detection is performed for longer time period, idle_wait[9:0]([idle _wait_l/h:b0 0x17/18(1-0)] can be used. by setting idle_wait [9:0], averaging period longer than the period (for example, ad conversion16 s, 8 times average setting 128 s) can be possible. this function can be used for idle determination ? by counting times when average ed value becomes smaller than cca threshold defined by [cca_level: b0 0x13] register. when counting exceed idle_wait [9:0], idle is determined. if average ed value exceeds cca threshold level, imemediately ?busy? is determined without wait for idle_wait [9:0] period. the following timing chart is idle detection setting idle_wait[9:0]. [ed value 8 timesv average idle detection case] [condition] cca normal mode adc_ck_sel ([adc_clk_set: b0 0x08(4)])=0b1 (2mhz) ed_avg[2:0] ([ed_ctrl: b0 0x1b(2-0)])=0b011 (ed value 8 times average) idle_wait[9:0] ([idle_wait_l/h: b0 0x17/18(1-0)])=0b00_0000_0011 (idle detection period 48 s) cca_en [note] 1. after issuing cca command, transit into no-input state, and exit this state after filter stbilization. 2. when the iput level chnge from no-input to -80dbm, it takes around 32 s for indicating -80dbm ed value. ed value (internal signal) cca_rslt[1:0] [cca_cntrl: b0 0x15(1-0)] cca_done [cca_cntrl: b0 0x15(2)] [cca_cntrl: b0 0x15(4)] ed_value[7:0] [ed_rslt: b0 0x16] ed value averaging period (128 s) 0b10 (cca on-going) ed1 ed8 ed2 ed7 ed9 ed10 ed11 filter stabilization 16 to 32 s ad conversion (16 s) idle detection period ed (0-7) 0b00 (idle) invalid averaging cca execution period (max.32 s+128 s+48 s=208 s) 0x001 0x000 0x002 0x003 (48 s) < cca_th_lv b0 0x13 ed0 ed ed ed (1-8) (2-9) (3-10) idle_wait[9:0] [idle_wait_l/h:b0 0x17/18] idle_wait start (average ed value < cca_th_lv) continue for ad conversion period 3 times (48 s), then idle is determined.
fedl7396a/b/e-07 ml7396a/b/e 52/140 [ed value 1time idle detection case] [condition] cca normal mode adc_ck_sel ([adc_clk_set: b0 0x08(4)])=0b1 (2mhz) ed_avg[2:0] ([ed_ctrl: b0 0x41(2-0)])=0b000 (ed value 1 time average) idle_wait[9:0] ([idle_wait_l/h:b0 0x1718(1-0 )])=0b00_0000_1110 (idle detection period 224 s) 0b10 (on-going) ed1 ed13 ed2 ed14 cca_en ed value average period (16 s) [cca_ctrl: b0 0x15 (4)] ed (0) 0b00 (idle) invalid do not average cca execution period (max.32 s+16 s+224 s=272 s) 0x001 0x000 0x002 idle detection period (224 s) < cca_th_lv ed (1) ed (2) ed3 0x00c 0x00d 0x00e ed (12) ed (13) ed (14) if idle_wait=0x000, idle is detection here. ed0 filter stabilization 16 to 32 s ad conversion (16 s) ed value (internal signal) ed_value[7:0] [ed_rslt: b0 0x16] idle_wait[9:0] [idle_wait_l/h;b0 0x17/18] cca_rslt[1:0] [cca_cntrl: b0 0x15(1-0)] cca_done [cca_cntrl:b0 0x15(2)] (average ed value < cca_th_lv) continue for ad conversion period 14 times (224 s ) , then idle is determined.
fedl7396a/b/e-07 ml7396a/b/e 53/140 c cca operation during diversity (1) cca operation during diversity search during diversity search, if cca command is issued, diversity terminated and cca starts. upon cca starting, antenna is fixed to the default value (*1), maintaining until next diversity search. however, if tx_ant_en ([2div_rslt:b0 0x72(5)])=0b1 is set, antenna is specified by tx_ant ([2div_rslt:b0 0x72(4)]) and maintaining until next diversity search. after cca completion, if sfd is not detected during diversity search time specified by search_time[6:0] ([2div_search:b0 0x6f(6-0)]) (default approx. 330 s), diversity search will be executed again. if sfd is detected during cca or after cca completion, continuing receive state and diversity search is not executed. * 1 : please refer the each table of ?antenna switching function? in ?diversity function?. (upper setting in the "rx" state column) after cca completion, if sfd is not detected during diversity search time, diversity search is executed again. maintaining the antenna during diversity search time. (default: 330 s) when tx_ant_en=0b1, the antenna is switched to the specified by tx_ant. when tx_ant_en=0b0 , if sfd is detected, maintaining receive state. the antenna is initialized to ant1. [note] when executing cca during diversity search, set the waiting taimer for waiting for caa completion interrupt (int[08] group2). since cca executing timing is same as the diversity search completion, cca completion interrupt may not be notified. when timeout occurs, the latest result is stored into cca_rslt[1:0] ([cca_cntrl:b0 0x15(1-0)]). in this case, if executing cca again, set cca_loop_stop ([cca_cntrl:b0 0x15(6)])=0b1 before issuing cca command. for waiting timer setting, please refer to the cca execution time described in "normal mode". for details of the cca execution flow during diversity search, please refer to "cca operation during diversity" in the ?flow charts?. during cca operarion, rx operation is performed at the same time. even if cca_done is not notified, sfd detection interrupt (int[11] group2), rx fifo access error interruptio n (int[14] group2), fifo-full interrupt (int[05] group1), fifo0/1 rx completion interrupt (int[18]/[19] group3), or fifo0/1 crc error interrupt (int[20]/[21] group3) may be notified. for details of the diversity function, please refer to "diversity function". ant_sw cca_en diversit y search cca cca_done diversit y search
fedl7396a/b/e-07 ml7396a/b/e 54/140 (2) during diversity search, before rx_on state, cca is performed if diversity on setting and cca operation setting are enabled before rx_on state, after rx_on state transition, diversity search will not perform, but cca will start. after cca completion, if sfd is not detected during diversity search time specified by search_time[6:0] ([2div_search:b0 0x6f(6-0)]) (default approx. 330 s), diversity search wil be executed. if sfd is detected during cca or after ccacompletion, continuing receive state and diversity search is not executed. when tx_ant_en=0b1, maintaining the antenna during diversity search time. (default: 330 s) ant_sw cca_en cca_done cc a diversit y search after cca completion, if sfd is not detected during diversity search time, diversity search is executed again. the antenna is switched to the specified by tx_ant. when tx_ant_en=0b0 , the antenna is initialized to ant1. if sfd is detected, maintaining receive state. rx_on 2div_done
fedl7396a/b/e-07 ml7396a/b/e 55/140 i sfd detection function ml7396 family supports the ?start frame of delimiter? (sfd) recognition function. by having 2 sets of sfd pattern strage area, it is possible to detect ieee 802.15.4g sfd patterns valied by ?mrfskfsd setting? and ?fec scheme?. for more details, please refer to ieee 802.15.4g standard. note: the default value of both sfd#1 and sfd#2 (bank0 0x3a to 0x41) are set to the ieee 802.15.4d sfd (1byte:0xa7). n ieee802.15.4g standard, 4 sfd pattern (each 2 bytes) is defined according to sfd group defined by phymrfsksfd and fec scheme (coded, uncoded). a ccording to the setting to mrfsksfd ([packet_mode_set:b0 0x45(6)]) and fec_en ([fec_crc_set:b0 0x46(6)]), sfd pattern to be added tx packet and sfd pattern to be received in rx packet are selected from sdf pattern #1 and sfd pattern #2 as following tables. sfd pattern #1 is defined by [sfd1_set1:b0 0x3a] to [sfd1_set4:b0 0x3d] registers and sfd pattern #2 is defined by [sfd2_set1:b0 0x3e] to [sfd2_set4:b0 0x41] registers. (1) tx sfd length is shorter than or equal to 2 bytes. (ieee 802.15.4g format) mrfsksfd fec_en 0 1 0 sfd1[15:0] sfd2[15:0] 1 sfd1[31:16] sfd2[31:16] sfd length is longer than or equal to 3 bytes. (original format mrfsksfd fec_en 0 1 0/1 sfd1 [31:0] sfd2 [31:0] (2) rx if sfd length is shorter than or equal to 2 bytes and fec_en=0b1, it is possible to serach two sfd patterns. according to the matching pattern, fec is performed. otherwise serach one pattern and the data following sfd are processed as uncoded. sfd length shorter than or equal to 2bytes. (ieee 802.15.4g format) sfd pattern fec_en mrfsksfd uncoded coded sfd detect data process after sfd 1 0 sfd1 [15:0] sfd1 [31:16] uncoded or coded if pattern match with coded pattern, fec is performed. if pattern match with uncoded pattern, fec is not performed 1 1 sfd2 [15:0] sfd2 [31:16] uncoded or coded if pattern match with coded pattern, fec is performed. if pattern match with uncoded pattenr, fec is not performed. 0 0 sfd1 [15:0] - uncoded determined as uncoded 0 1 sfd2 [15:0] - uncoded determined as uncoded
fedl7396a/b/e-07 ml7396a/b/e 56/140 sfd length is longer than or equal to 3bytes. (original format) sfd pattern fec_en mrfsksfd uncoded coded sfd detect process following to sfd 1 0 sfd1 [31:0] - uncoded determined as uncoded 1 1 sfd2 [31:0] - uncoded determined as uncoded 0 0 sfd1 [31:0] - uncoded determined as uncoded 0 1 sfd2 [31:0] - uncoded determined as uncoded when using ieee 802.15.4g (2bytes sfd), recommended configuration will be as following table. register name address (bank 0) setting value sfd1_set1 0x3a 0x09 sfd1_set2 0x3b 0x72 sfd1_set3 0x3c 0xf6 sfd1_set4 0x3d 0x72 sfd2_set1 0x3e 0x5e sfd2_set2 0x3f 0x70 sfd2_set3 0x40 0xc6 sfd2_set4 0x41 0xb4
fedl7396a/b/e-07 ml7396a/b/e 57/140 auto_ack function ml7396 family supports auto_ack function to assist mcu operation in acknowledge packet (hereafter ack packet) transmission. followings are detail of the auto_ack function. [notes when using auto_ack function] 1. auto_ack function can not be used with fec function, please set fec_en ([fec/crc_set:b0 0x46(6)])=0b1. when mcu handls ack packet, fec function can be used. 2. when tx packet and rx packet use diferent fcs length, especially note on the following; if transmissting ack packet before reading out rx data from fifo, tx packet fcs length will be applied to the unread rx data stored into fifo. therefore, rx data can not be read out correctly. under this case, before start to read rx data, forcibly set rx packet fcs length by using [fec/crc_set:b0 0x46] register. (above condition will meet when the data packet uses 32b it fcs and ack packet uses 16bit fcs. since ml7396 fammily does not support 32bit fcs ack packet.) *ack transmission (mcu requests transmitting ack packet) 1) analyzing frame control field in rx data, and if ack request bit is set to 0b1, then obtain sequence number from rx data. 2) after rx completion, performing crc check and if fcs is ok, then transit to tx_on state automatically for ack packet transmission preparation. (at this time, rx completion interrupt (int[18]/[19] group3) will be generated.) 3) mcu analyzes address field and pending data in received data, and it decide to transmit ack packet, set ack packet to [ack_frame1:b0 0x53] and [ack_frame2:b0 0x54] registers. note: it is dpossible to determine ack packet transmittion by reading mac header. therefore ack packet setting is possible before rx completion. if there is a pending data, the frame pending bit should be set to 0b1 by [ack_frame1:b0 0x53] register. 4) after completing tx_on state transition, auto_ack ready interrupt (int[24] group4) will be generated. after confirming ack_ready interrupt, set ack_send ([auto_ack_set:b0 0x55(1)])=0b1 . 5) transmitting ack packet frame control field is filled with the setting data into [ack_frame1:b0 0x53] and [ack_frame2:b0 0x54] registers. sequence number field is automatically filled with sequence number obtained from received data. 6) after ack packet transmission is completed, tx completion interrupt (int[16]/[17] group 3) will be generated. note: rf status keeps tx_on state, if return to idle state, set set_trx ([rf_status:b0 0x6c(3-0)]) =0b1000 (trx_off). *ack transmission (mcu requests to stop ack packet transmission) 1) analyzing frame control field in rx data, and if ack request bit is set to 0b1, then obtain sequence number from rx data. 2) after rx completion, performing crc check and if fcs is ok, then transit to tx_on state automatically for ack packet transmission preparation. (at this time, rx completion interrupt (int[18]/[19] group3) will be generated.) 3) after completing tx_on state transition, auto_ack ready interrupt (int[24] group4) will be generated. 4) mcu analyzes address field and pending data in received data, and it decide not to send ack packet, issuing phy reset by [rst_set:b0 0x01]=0x88 and then set ack_stop ([auto_ack_set:b0 0x55(0)])=0b1. ml7396 family aborts ack packet and rf status will be back to trx_off state automatically.
fedl7396a/b/e-07 ml7396a/b/e 58/140 5) set ack_stop ([auto_ack_set:b0 0x46(0)])=0b0. if ackauto_ack ready interrupt (int[24] group4) is already generated, please clear the interrupt. *ack transmission (ack packet transmission using ack timer) condition: auto_timer_en ([ack_timer_en:b0 0x52(0)])=0b1. 1) analyzing frame control field in rx data, and if ack request bit is set to 0b1, then obtain sequence number from rx data. 2) after rx completion, performing crc check and if fcs is ok, then transit to tx_on state automatically for ack packet transmission preparation. (at this time, rx completion interrupt (int[18]/[19]) will be generated.) 3) after completing tx_on state transition, ack timer starts counting and auto_ack ready interrupt (int[24] group4) will be generated. 4) after elapsing the period defined by [ack_timer_l/h:b0 0x50/51] registers, ack packet will be transmitted. 5) after ack packet trnasumission is completed, tx completion interrupt (int[]16)/[17] group3) will be generated. note: rf status keeps tx_on state, if return to idle state, set set_trx ([rf_status:b0 0x6c(3-0)]) =0b1000 (trx_off). [additional function] ? by setting cca_auto_en ([cca_cntrl:b0 0x15(7)])=0b1, it is possible to execute cca operation automatically for ack packet transmission. *ack reception condition: auto_rx_en ([auto_ack_set:b0 0x55(6)])=0b1. 1) after competing transmission of data packet with ack request, tx completion interrupt (int[16]/[17] group3) will be generated, then transit to rx_on state au tomatically for ack packet to reception. 2) after rx completion for ack packet, rx completion interrupt (int[18]/[19]) will be generated. note: rf status keeps rx_on state, if return to idle state, set set_trx ([rf_status:b0 0x6c(3-0)]) =0b1000 (trx_off). *ack reception (terminate ack packet waiting) condition: auto_rx_en ([auto_ack_set:b0 0x55(6)])=0b1. 1) after competing transmission of data packet with ack request, tx completion interrupt (int[16]/[17] group3) will be generated, then transit to rx_on state au tomatically for ack packet to reception. 2) if mcu determined to terminate ack packet wait ing, set ack_stop ([auto_ack_set:b0 0x55(0)]) =0b1. ml7396 family aborts ack packet waiting and rf status will be back to trx_off state automatically.
fedl7396a/b/e-07 ml7396a/b/e 59/140 address filtering function: ml7396 family has a function to receive rx packet which mac h eader has specific code at yellow highlighted field in the mac header (ieee802.15.4) as below. by using [addfil_cnt rl:b2 0x20] register, comparing field is selected from panid, 64bit address, 16bit short address or i/g bit. each specific code are defined by [panid_l:b2 0x61] to [sht_addr1_h:b2 0x6e] registers. source address is out of comparing target. byte : 2 1 0 / 2 0/2/8 0 / 2 0/2/8 variable 2 frame sequence destination destination source source frame frame control number pan address pan address payload chack identifier identifier sequence mac mac payload footer bits : 0-2 3 4 5 6 7-9 10-11 12-13 14-15 frame security frame ack. pan-id dest. source type enabled pending req. addressing addressing mode mode addressing fields mac header reserved frame version compressio n fig. mac header and frame control field destination addressing mode 00: beacon or ack packet (beacon packet is always received, ack packet reception can be selectable) 01: reserved (does not receive) 10: 16 bits address 11: 64 bits address destination.pan-id 0xffff: broadcasting, then always receive this packet regardless to address mode. 16 bits address mode: receive packet if pan_id (setting vslue) is matched. 64 bits address mode: ignoring this field. destination address 16 bit address mode: receive packet only if short address (setting value) is matched. 64 bit address mode: receive packet only if 64 bits addr ess is matched, or i/g bit is set to 0b1 (multicast). references: when address filtering function is enabled, packet analisis will be executed. therefore when using rx_ack cancel ([auto_ack_set:b0 0x55(7)]) function, address filtering function should be enabled, since packet anlisis is need uted to detect ack packet. for details, please refer to [auto_ack_set:b0 0x55] register.
fedl7396a/b/e-07 ml7396a/b/e 60/140 when address fields are mismatch with set value, following procedure is determined by the setting to addfil_ng_set ([packet_mode_set:b0 0x45(5)]) and packet discard completion interrupt (int[03] group1) timing is defined by addfil_idle_det ([packet_mode_set:b0 0x45(0)]). addfil_ng_set (bit5) 0b1: when address-mismatch is detected, discarding rx data after rx completetion. 0b0: when address-mismatch is detected, discarding rx data immediately. addfil_idle_det (bit0) 0b1: after discarding rx data perform cca and ?idle? is detected, int[03] will be generated. 0b0: after discarding rx data, int[ 03] will be generated immediately. when rx data is discarded, adding to int[03] generation, discarded packet can be counted up to 1023 and result stored in [discard_count0:b2 0x6f] and [discard_count1:b2 0x70] registers. [note] when using address filtering function while fec function is enabled, if int[03] is notified. phy reset by [rst_set:b0 0x01] should be required. if not issuing phy reset, after that, ml7396 can not receive packet with address match also. [address filtering function overview] frame control field device a device b device c data packet (tx) tx rx data packet (rx) data packet (rx) address fields are match with setting value, maintaining rx.. address fields are mismatch with setting value. rx data will be discarded ack packet (rx) rx tx ack packet (tx) if addfil_ng_set=0b0, this field will not be received tx rx int[03] timing when addfil_ng_set=0 and addfil_idle_det =0 int[03] timing when addfil_idle_det=1 cca detection (idle detect) int[03] timing when addfil_ng_set=1 and addfil_idle_det =0
fedl7396a/b/e-07 ml7396a/b/e 61/140 [interrupts timing when using int_tim_ctrl] by setting int_tim_ctrl ([pll_mod/dio_sel:b0 0x69(6)]), it is possible to select interrupt timing during address filtering mode. according to the addfil_ng_set or addfil_idle_det setting and crc result in the rx packet, interrupt generation timings of packet discard completion interrupt, crc error interrupt, and cca completion interrupt, will become as below figures. setting 1 setting 2 setting 3 setting 4 setting setting register case1 case2 case3 case4 case5 case6 case7 case8 discard packet after address mismatch addfil_ng_set=0b0 o o - - o o - - discar packet after address mismatch and rx completion addfil_ng_set=0b1 - - o o - - o o execute cca after address mismatch addfil_idle_det=0b 1 - - - - o o o o crc_ok - o - o - o - o - input crc_ng - - o - o - o - o packet discard cpmpletion interrupt int[3] [int_source_grp1] o o o o o o o o crc error interrupt int[21/20] [int_source_grp3] o o - o o o - o interrupt result cca completion interrupt int[8] [int_source_grp2] - - - - o o o o (1) when int_tim_ctrl=0b0 (timing is comatible with ml7396) case1 to : 1111ns setting 1 case2 to : 1111ns case3 setting 2 case4 and at same time case5 to : 555ns setting 3 case6 to : 555ns case7 to : 555ns setting 4 case8 to : 555ns (2) when int_tim_ctrl=0b1 (ml7396b timing) case1 : 1111ns setting 1 case2 to : 1111ns case3 setting 2 case4 and at same time case5 setting 3 case6 case7 setting 4 case8 mac hdr phy hdr data cca (idle detection)
fedl7396a/b/e-07 ml7396a/b/e 62/140 interrupt generation function ml7396 family supports intterupt generation function. when interrupt occurs, sintn pin (#10) will become ?low? to notify interrupt to the host mcu. interrupt elements are divided into 4groups, [int_source_grp1:b0 0x24] to [int_source_grp4:b0 0x27]. each interrupt elements can be masked by using [int_en_grp1:b0 0x2a] to [int_en_grp4] registers. note: if one of unmask interrupt event occurs, sintn maintains ?low?. c interrupt events table each interrupt events is described as belo table. group name function: int[25] pll unlock interrupt int_source_grp4 int[24] auto_ack ready interrupt int[23] fifo1 tx data request accept completion interrupt int[22] fifo0 tx data request accept completion interrupt int[21] fifo1 crc error interrupt int[20] fifo0 crc error interrupt int[19] fifo1 rx completion interrupt int[18] fifo0 rx completion interrupt int[17] fifo1 tx completion interrupt int_source_grp3 int[16] fifo0 tx completion interrupt int[15] tx fifo access error interrupt int[14] rx fifo access error interrupt int[13] tx length error interrupt int[12] rx length error interrupt int[11] sfd detection interrupt int[10] rf state transition completion interrupt int[09] diversity search completion interrupt int_source_grp2 int[08] cca completion interrupt - no function - no function int[05] fifo_full interrupt int[04] fofo_empty interrupy int[03] packet discard competion interrupt int[02] vco calbration completion interrupt int[01] reserved int_source_grp1 int[00] clock stabilization completion interrupt
fedl7396a/b/e-07 ml7396a/b/e 63/140 c interrupt generation timing in each interrupt generation, timing from reference point to interrupt interrupt generation (nitification) are described in the following table. timeout procedure for interrupt notification waiting, are also described below. [note] (1)the values are decribed in units of ?symbol time? in the below table is the value at 100kbps. if using other data, please us e 20, 5, and 2.5 for 50kbps, 200kbps, and 400kbps, respectively. (2)below table uses the following format of tx/rx data. 24 byte (3)even if each interrupt notification is masked, in case of in terrupt occurrence, interrupt elements are stored internnaly. therefore, as soon as interrupt notification is unmasked, interrupt will generate. interrupt notification reference point time from reference point to interrupt generation or interrupt generation timing resetn release (upon power-on) 660 s int[0] clk stabilization completion sleep release (recovered from sleep) 660 s int[1] int[2] vco calibration completion vco calibration start 230 s int[3] packet discard completion during address filtering function sfd detection (1)if addfil_ng_ set([packet_mode_set:b0 0x45(5)]) =0b0, the right timing to address mismatch detection. (2)if addfil_ng_set([packet _mode_set:b0 0x45(5)]) =0b1, (when fec is disabled) 28byte (length to crc) * 8bit * 10(symbol time) + process delay(5.55 s) =2245.55 s (when fec is enabled) 28byte (length to crc) * 2 * 8bit *10(symbol time) + process delay(315.55 s) =4795.55 s (tx) tx_on command (* 1) empty trigger level is set to 0x02 (when fec is disabled) 37 byte (preamble to 23th data) * 8bit * 10 (symbol time) =2960 s (when fec is enabled) {12byte (preamble to sfd) + 25byte(length to 23th data) * 2} * 8bit* 10(symbol time) + rf wake-up & process delay (106 s) =5066 s int[4] fifo-empty detection (rx) by fifo read, remaining fifo data is under trigger level (tx) by fido write, fifo usage exceeds trigger level int[5] fifo-full detection (rx) sfd detection full trigger level is set to 0x05 (when fec is disabled) 8byte (length + 6 th data) * 8bit * 10(symbol time) =640 s (wwhen fec is enabled) 8byte (length + 6 th data) * 8bit * 2 * 10(symbol time) + process delay(305 s) =1585 s (int[6]) - (int[7]) - (* 1) befor issuing tx_on, writing full-length tx data into a fifo. 2 byte 2 byte 10 byte 2 byte sfd crc length preamble user data
fedl7396a/b/e-07 ml7396a/b/e 64/140 interrupt notification reference point time from reference point to interrupt generation or interrupt generation timing int[8] cca completion cca execution start (1)normal mode {ed value calculation averaging time + idle_wait setting [idle_wait_l/h:b0 0x17/18] + 2 (filter stbilization)} * a/d conversion time (2) idle detection mode c idle detection case {ed value calculation averaging time + idle_wait setting [idle_wait_l/h:b0 0x17/18] + 2(filter stbilization)} * a/d conversion time c busy detection case (ed value calculation averaging tim+ 2(filter stbilization)) * a/d conversion note: a/d conversion time can be changed by adc_clk_set (adc_clk_set:b0 0x08(4)). adc conversion time= 17.7 s (1.8mhz), 16 s (2.0mhz) note: when executing cca during diversity, set the abort timer for cca completion notification. when cca is run during diversity, since there is a case cca completion is not notified. int[9] diversity search completion - diversity search completion tx_on command (idle) 122 s (rx) 89 s rx_on command (idle) 136 s (tx) 142 s trx_off command (tx) 410 s (rx) 11 s int[10] rf state transition completion force_trx_off command (tx) 410 s (rx) 10 s int[11] sfd detection - sfd detection int[12] rx length error sfd detection 80 s int[13] tx length error - writing tx data to a fifo int[14] rx fifo access error - (1).receiving 3 rd packet with remaining rx dara in both fifo0 and fifo1 (2) overfolow occurs because fifo read is too slow (3) underflow occurs because too many fifo data is read int[15] tx fifo access error - (1) writing 3 rd packet with remaining tx data in both fifo0 and fifo1 (2) fifo overflow when writing (3) fifo underflow (or no data) when transmitting int[16] int[17] fifo0/fifo1 tx completion tx_on command (* 1) (when fec is disabled) 40byte (preamble to crc) * 8bit * 10(symbol time) + rf wake-up & process delay(154 s) =3354 s (when fec is enabled) {12byte (preamble to sfd) + 28byte (length to crc) * 2} * 8bit * 10(symbol time) + rf wake-up & process delay(224 s) =5664 s (* 1) befor issuing tx_on, writing full-length tx data into a fifo.
fedl7396a/b/e-07 ml7396a/b/e 65/140 interrupt notification reference point time from reference point to interrupt generation or interrupt generation timing int[18] int[19] fifo0/fifo1 rx completion sfd detection (when fec is disabled) 28byte (length to crc) * 8bit * 10(symbol time + process delay(5 s) =2245 s (when fec is enabled) 28byte (length to crc) * 2 * 8bit * 10(symbol time) + process delay(315 s) =4795 s int[20] int[21] fifo0/fifo1crc error detection sfd detection (with fec disabled) 28byte (length to crc) *8bit * 10(symbol time) + process delay(5 s) =2245 s (with fec enabled) 28byte (length to crc) * 2 * 8bit * 10(symbol time + process delay(315 s) =4795 s int[22] int[23] fifo0/fifo1 tx data request accept completion - after full-length data are written into a fifo int[24] autoack ready rx completion 92us int[25] pll unlock detection - (tx) during tx after pa enable (rx) during rx after rx enable
fedl7396a/b/e-07 ml7396a/b/e 66/140 c clearing interrupt condition the following table shows the condition of clearing each interrupt. interrupt notification requirements for clearing interrupt int[0] clk stabilization completion after the interrupt generation int[1] reserved int[2] vco calibration completion after the interrupt generation int[3] packet discard completion during address filtering function after the interrupt generation int[4] fifo-empty detection after the interrupt generation (must clear before the next fifo-empty trigger timing) int[5] fifo-full detection after the interrupt generation (must clear before the next fifo-full trigger timing) int[6] - int[7] - int[8] cca completion after the interrupt generation (must clear before the next cca execution) * clearing interrupt erases cca result as well int[9] diversity search completion after rx completion interrupt(int[18/19]), must cleare with rx completion interrupt * during receive stare, clearing is prohibited. int[10] rf state transition completion after the interrupt generation int[11] sfd detection after the interrupt generation int[12] rx length error after the interrupt generation int[13] tx length error after the interrupt generation int[14] rx fifo access error after the interrupt generation int[15] tx fifo access error after the interrupt generation (must clear before the next packet transmission) int[16/17] fifo0/fifo1 tx completion after the interrupt generation (must clear before the next packet transmission) int[18/19] fifo0/fifo1 rx completion after the interrupt generation (must clear before the next packet reception) int[20/21] fifo0/fifo1crc error detection after the interrupt generation * clearing interrupt erases crc result (crc_rslt1/0). int[22/23] fifo0/fifo1 tx data request accept completed after tx completion interrupt (int[16/17]) (must clear before the next packet transmission) * during transmit state, clearing is prohibited. int[24] autoack ready after the interrupt generation int[25] pll unlock detection after the interrupt generation (must clear before the next packet transmission or reception)
fedl7396a/b/e-07 ml7396a/b/e 67/140 temperature measurement function ml7396 family has temeperature measurement function. this temperature information can be from a_mon pin (#24) as analog output or digital information using [temp_mon:b0 0x79] register. analog or digital can be switched by [rssi/temp_out:b1 0x03] register. notes: 1) please do not set temp_out ([rssi/temp_out:b1 0x03(4)]) and temp_adc_out ([rssi/temp_out:b1 0x03(5)]) at the same time. correct value reading may not be guaranteed. 2) when temp_adc_out is set, packet data is not able to receive normally. [analog output] ml7396 family has current source circuits and its current flow through 75k ? to a_mon pin (#24). from voltage information, temperature information can be obtained. current from currwnt source circuits are 10 a at 25 ? c. following formula can be used to calculate temperature from the current. itemp = (273+ temp) / (273+25) * 10 ( a) therefore, if 75k ? resister is connected, temprature can be calculated usng following formula. vamon = (273+ temp) / (275+25) * 10e-6 * 75000 if temprature is -40 ? c to +85 ? c, vamon will be 0.59v to 0.9v. therefore temperature can be calculated from voltage using following formula. temp = vamon * 397.3 - 273 [digital output] digital temperature information is using 6bits adc to conver t from the above analog information. internally, 4samples information are added and indicates as 8bits information in [t emp_mon:b0 0x79] register. ignorimg low 2 bits, upper 6bits are used for average temperature information. temperature information is updated every 17.8 s. (if 2mhz is selected in [adc_clk_set:b0 0x08] register, it is updated every 16 s)
fedl7396a/b/e-07 ml7396a/b/e 68/140 ramp control function ml7396 has ramp control function. this function will contribute reducing spurious emission when transmission is terminated. ramp control will be executed when switchin g tx_on to trx_off state and tx_on to rx_on state. the following are control bits retative with ramp control function. txoff_ramp_en ([ramp_cntrl:b2 0x2c (4)]): ramp control enable bit tim_tx_off1[7:0] ([tx_off_add1:b1 0x55(7-0)]): ramp down timing adjustment when transitioning from tx_on to trx_off. tim_rx_on2[2:0] ([rx_on_adj2:b1 0x3f(6-4)]): rx_on timi ng adjustment when transitioning from tx_on to rx_on tim_tx_off2[5:0] [2div_gain_contrl:b0 0x6e(7-2)]): ramp down timing adjustment when transitioning from tx_on to rx_on. [operation overview] (1) ramp down timing when transitioning from tx_on to trx_off [condition] txoff_ramp_en ([ramp_cntrl:b2 0x2c(4)]) =0b1 tim_tx_off1[7:0] ([tx_off_add1:b1 0x55(7-0)] =0xb4(400 s), 0x42 (150 s) tim_rx_on2[2:0] ([rx_on_adj2:b1 0x3f(6-4)]) =0b011 tim_tx_off2[5:0] ([2div_gain_contrl:b0 0x6e(7-2)]) =0b1011_01 trx_off command * set_trx[3:0] ([rf_status:b0 0x6c(4-0)]) =0b1000 scen pa enable tx enable rx enable transmitter power 3 s (tim_tx_off1+1) * 2.22 s = 401.82 s
fedl7396a/b/e-07 ml7396a/b/e 69/140 (2) ramp down timing when transitioning from tx_on to rx_on [condition] txoff_ramp_en ([ramp_cntrl:b2 0x2c(4)]) = 0b1 tim_tx_off1[7:0] ([tx_off_add1:b1 0x55(7-0 )]) =0xb4 (400 s) tim_rx_on2[2:0] ([rx_on_adj2:b1 0x3f(6-5)]) =0b011 tim_tx_off2 ([2div_gain_contrl:b0 0x6e(7-2 )]) =0b1011_01 rx_on command * set_trx[3:0] ([rf_status:b0 0x6c(4-0)]) =0b0110 scen pa enable tx enable rx enable transmitter power 3 s (tim_tx_off2+1) * 2.22 s = 102.12 s (tim_rx_on2+1) * 8.88 s + 2.22 s =37.74 s pll_rst_i
fedl7396a/b/e-07 ml7396a/b/e 70/140 (3) ramp down timing when transitioning from tx_on to trx_off (ramp control disabled) [condition] txoff_ramp_en ([ramp_cntrl:b2 0x2c(4)]) =0b0 tim_tx_off1[7:0] ([tx_off_add1:b1 0x55(7-0)]) =0xb4 (400 s) tim_rx_on2[2:0] ([rx_on_adj2:b1 0x3f(6-4)]) =0b011 tim_tx_off2 ([2div_gain_contrl:b0 0x6e(7-2)]) =0b1011_01 trx_off command * set_trx[3:0] ([rf_status:b0 0x6c(4-0)]) =0b1000 scen tx enable transmitter power pa enable rx enable 3 s 24.42 s
fedl7396a/b/e-07 ml7396a/b/e 71/140 (4) ramp down timing when transitioning from tx_on to rx_on (ramp control disabled) [condition] txoff_ramp_en ([ramp_cntrl:b2 0x2c(4)]) =0b0 tim_tx_off1[7:0] ([tx_off_add1:b1 0x55(7-0)]) =0xb4 (400 s) tim_rx_on2[2:0] ([rx_on_adj2:b1 0x3f(6-4)]) =0b011 tim_tx_off2[5:0] ([2div_gain_contrl:b0 0x6e(7-2)]) =0b1011_01 rx_on_adj[7:0] ([rx_on_adj:b2 0x22(7-0)]) =0x0a rx_on command * set_trx[3:0] ([rf_status:b0 0x6c(4-0)]) =0b0110 scen tx enable transmitter power pa enable 3 s rx enable 24.42 s (rx_on_adj+1) * 8.88 s = 97.68 s
fedl7396a/b/e-07 ml7396a/b/e 72/140 rf configuration programming channel frequency maximum 16 channels can be selected. (ch#0 to ch#15) cahnnel allocation is defined by channel #0 frequency specified by [ch0_fl:b0 0x48], [ch0_fm:b0 0x49], [ch0_fh:b0 0x4a] and [ch0_na:b0 0x4b] registers, and channel spacing specified by [ch_space_l:b0 0x4c] and [ch_space_h:b0 0x4d] registers. 16 channels can be enabled or disabled by [ch_en_l:b0 0x2e] and [ch_en_h:b0 0x2f] registers. rf channel is set as channel number (#0 to #15) at [ch_set:b0 0x6b] register notes: 1) frequency range (from ch#0 to ch#15) can not include integer multiple of 36mhz. (ex: 900mhz, 936mhz) 2) the channel frequency must meet the following condition. if the following condition can not meet, please change the channel #0 frequency or disabling channels that can not meet the condition by [ch_en_l:b0 0x2e] and [ch_en_h:b0 0x2f] register. 36mhz * n + 2.2mhz channel frequency < 36mhz * (n+1) ? 500khz * n=integer 3) if the above condition can not be met, expected channel frequency is not functional or pll may not be locked. [channel frequency programming flow] start set ch#0 frequency [ch0_fl:b0 0x48] [ch0_fm:b0 0x49] [ch0_fh:b0 0x4a] [ch0_na:b0 0x4b] set ch spacing [ch_space_l:b0 0x4c] [ch_space_h:b0 0x4d] ch#0 to ch#15 frequency allocation will be defined. set ch enable/disable [ch_en_l:b0 0x2e] [ch_en_h:b0 0x2f] select ch number [ch_set:b0 0x6b] end
fedl7396a/b/e-07 ml7396a/b/e 73/140 c programming channel#0 frequency channel #0 frequency can be set by [ch0_fl:b0 0x48], [ch0_fm:b0 0x49], [ch_fh:b0 0x4a] and [ch_na:b0 0x4b] registers. each setting parameters for channel #0 can be calculated using the following formula. n = f / f ref / p (integer part) a = f / f ref - n * p (integer part) f = {f / f ref - (n * p + a)} * 2 20 (integer part) [note: useing 20bit circuit] here f : channel #0 fequency f ref : pll reference frequency (input clock=36mhz) p : dual modulus parameter (fixed to 4) n : n-counter parameter a : a-counter parameter f : f-counter parameter and frequency error can be calculated using the following formula. ferr = f - [f ref * {(n * p + a) + f/2 20 }] [example] when set channel #0 frequecy to 923.1mhz, the calculations are as follows. (f ref = 36mhz) n = 923.1mhz / 36mhz / 4 (integer part) = 6 a = 923.1mhz / 36mmhz- 6 * 4 (integer part) = 1 f = {923. 1mhz / 36mhz - (6 *4 + 1)} *2 20 (integer part) = 672836 (0xa4444) therefore [ch0_fl:b0 0x48] = 0x44 [ch0_fm:b0 0x49] = 0x44 [ch0_fh:b0 0x4a] = 0x0a [ch0_na:b0 0x4b] = 0x61 feuqency error will be ferr = 923. 1mhz - [36mhz * {(6 * 4 + 1) + 672836 / 2 20 }] = +31.7hz c programming channel pace channel space can be set by [ch_space_l:b0 0x4c] and [ch_space_h:b0 0x4d] registers. channel space is frequency space between centre frequency of given channel and that of adjacent channel. channel space setting value can be calculated using the following formula. ch_sp_f = {f sp / f ref } * 2 20 (integr part) [note: using 20bit circuit] here ch_sp_f : channel space setting f sp : channel space [mhz] f ref : pll reference frequency (input clock=36mhz) [example] when set channel space is 400khz, the calculation are as follow. (f ref = 36mhz) ch_sp_f = {0.4mhz / 36mhz} * 2 20 (integer part) = 11650 (0x2d82) therefore [ch_space_l:b0 0x4c] = 0x82 [ch_space_h:b0 0x4d] = 0x2d
fedl7396a/b/e-07 ml7396a/b/e 74/140 programming if frequency in order to support various data rate , rx filters have to be optimised. the rx filter can be selected according to the if frequency. if frequency can be set by using [if_freq_h: b1 0x0a] and [if_freq_l: b1 0x0b] registers. (default: 178.22khz) according to the rate[2:0] ([data_set:b0 0x47(2-0)]) setting and nbo_sel([data_set:b0 0x47(7)]) setting, if frequency will be multiplied automatically as following table. data rate nbo_sel 50kbps 100kbps 150kbps 200kbps 400kbps 0b0 x2 x4 x4 x6 x6 0b1 x2 x2 - x4 - if frequency value should be set as the multiplied if frequency corresponding to each data rate becomes the values described in the following table. data rate nbo_sel 50kbps 100kbps 150kbps 200kbps 400kbps 0b0 500khz 720khz 900khz 1300khz 2100khz 0b1 500khz 720khz - 1300khz - [notes] 1. nbo_sel=0b1 can not be set for the data rate other than 50kbps, 100kbps and 200kbps. 2. for 10kbps, 20kbps, 40kbps setting, please refer to the "initial register setting" file . if afc is used, if frequency setting in [if _freq_afc_h: b0 0x30] and [if_freq_afc_l: b0 0x31] registers will be used. if frequency setting for afc operation is same as normal operation. if cca is used to detect channel carrier power, required rx filter bandwidth may be different. [if _freq_cca_h: b1 0x0c] and [if_freq_cca_l: b1 0x57] registers must be used for cca purpose. during cca operation if frequency calculation becomes as below. data rate nbo_sel 50kbps 100kbps 150kbps 200kbps 400kbps 0b0 x2 x6 x8 x8 x8 0b1 x2 x2 - x6 - if frequency value for cca operation should be set as the multiplied if frequency corresponding to each data rate becomes the values described in the following table. data rate nbo_sel 50kbps 100kbps 150kbps 200kbps 400kbps 0b0 500khz 1500khz 1450khz 2000khz 2100khz 0b1 500khz 720khz - 1500khz - [notes] 1. nbo_sel=0b1 can not be set for the data rate other than 50kbps, 100kbps and 200kbps. 2. for 10kbps, 20kbps, 40kbps setting, please refer to the "initial register setting" file.. if frequency setting value can be calculated using the following formula. if_freq = {f if / f ref } * 2 20 (integr part) [note: using 20bit circuit] here if_freq : if frequency setting f if : if frequency [mhz] f ref : pll reference frequency (input clock=36mhz) [example] when set if frequency is 178.22khz, the calculation are as follow. (f ref = 36mhz) if_freq = {0.17822mhz / 36mhz} * 2 20 (integer part) = 5191 (0x1447) therefore [if_freq_h] = 0x14 [if_freq_l] = 0x47
fedl7396a/b/e-07 ml7396a/b/e 75/140 programming bpf band width for normal operation (including afc) and cca operation, optimized bpf setting are necessary. to compensating lsi variations, [bpf_adj_offset:b1 0x1e] register indicates individual cpmpensation value. according to the below tabl e, multiplying bpf_offset[6:0] ([bpf_adj_offse t:b1 0x1e(6-0)]) by the coefficient value corresponding to each data rate. if bpf_offset_pol ([bpf_adj_offset:b1 0x1e(7)] = 0b1, incraseing, otherwise (=0b0) decrasing to the default value corresponding each data rate. compensated value is set into [bpf_adj_h/l:b1 0x0e/0f] and [bpf_afc_adj_h/l:b0 0x32/33] registers for normal operation. for cca operation, set to [bf_cca_adj_h/l:b1 0x10/11] register. following tables show coefficient value and default valu e corresponfding to rate[2:0] ([data_set:b0 0x47(2-0)]) setting and nbo_sel([data_set:b0 0x47(7)]) setting [when nbo_sel=0b1] normal operation cca operation data rate [kbps] rate[2:0] [b0 0x47] coefficient value default value coefficient value default value 50 0b000 1.44 0x034b 1.44 0x034b 100 0b01 1 0x024a 0.48 0x0119 150 0b010 0.8 0x01d4 0.497 0x0122 200 0b010 0.554 0x0144 0.36 0x00d2 400 0b011 0.343 0x00c8 0.343 0x00c8 [when nbo_sel=0b0] normal operation cca operation data rate [kbps] rate[2:0] [b0 0x47] coefficient value default value coefficient value default value 50 0b000 1.44 0x034b 1.44 0x034b 100 0b01 1 0x024a 1 0x024a 150 0b010 - - - - 200 0b010 0.554 0x0144 0.48 0x0119 400 0b011 - - - - [example] condition: data rate is 100kbps, and [bpf_adj_offset:b1 0x1e] =0x91 [bpf_adj_h/l:b1 0x0e/0f] = 0x24a + 1 * (0x11) = 0x025b [bpf_afc_adj_h/l:b0 0x32/33] = 0x24a + 1 * (0x11) = 0x025b [bf_cca_adj_h/l:b1 0x10/11] = 0x119 + 0.48 * (0x11) = 0x0121 note: for 10kbps, 20kbps, 40kbps setting, please refer to the "initial register setting" file.
fedl7396a/b/e-07 ml7396a/b/e 76/140 programming gfsk modulation by setting gfsk_en ([data_set;b0 0x47(4)]) =0b1, gfsk modulation can be selected. c programming gfsk frequency deviation in gfsk modulation, frequency deviation can be set by [f_dev_l:b0 0x4e] and [f_dev_h:b0 0x4f] registers. frequency deviation setting value can be calculated using the following formula. f_dev = {f dev / f ref } * 2 20 (integer part) [note: using 20bit circuit] here f_dev : frequency deviation setting f dev : frequency deviation [mhz] f ref : pll reference frequency (input clock=36mhz) [example] when set frequency deviation is 50 khz at 100kbps, the calculation are as follow. (f ref = 36mhz) f_dev = {0.05mhz / 36mhz} * 2 20 (integer part) = 1456 (0x05b0) therefore [f_dev_l:b0 0x4e] = 0xb0 [ch_space_h:b0 0x4d] = 0x05 following table shows frequency deviation value with modulation index (m) =1 for each data rate. data rate register 50kbps 100kbps 150kbps 200kbps [f_dev_l:b0 0x4e] 0xd8 0xb0 0x44 0x60 [f_dev_h:b0 0x4f] 0x02 0x05 0x04 0x0b note: for 10kbps, 20kbps, 40kbps setting, please refer to the "initial register setting" file.
fedl7396a/b/e-07 ml7396a/b/e 77/140 c programming gaussian filter gaussian filter can be set by [gfil00/fsk_fdv1:b0 0x59] to [gfil11:b0 0x64] registers. bt value of gaussian filter and setting value to related registers are shown in the below tables. all setting values are described as hexadecimal value. remarks: setting values for bt=0.5 at 100kbps are set as initial values in registers related to gaussian filter, since initial values of [data_set:b0 0x47] register is gfsk enable and 100kbps setting. gaussian filter register setting (for 10kbps/20kbps/40kbps/50kbps/100kbps/150kbps/200kbps) (hex) register address: bit bt=1.0 bt=0.5 bt=0.4 bt=0.3 bt=0.25 [1:0] 0 0 0 0 1 [3:2] 0 0 0 0 1 [5:4] 0 0 0 1 1 gfil00 0x59 [7:6] 0 0 0 1 2 [3:0] 0 0 0 1 3 gfil01 0x5a [7:4] 0 0 1 2 4 [3:0] 0 0 1 3 5 gfil02 0x5b [7:4] 0 1 2 5 6 gfil03 0x5c [7:0] 00 01 03 06 07 gfil04 0x5d [7:0] 00 03 05 08 09 gfil05 0x5e [7:0] 00 05 08 0a 0a gfil06 0x5f [7:0] 00 09 0c 0c 0c gfil07 0x60 [7:0] 03 0f 0f 0e 0d gfil08 0x61 [7:0] 0b 15 13 10 0e gfil09 0x62 [7:0] 1d 1a 17 13 0f gfil10 0x63 [7:0] 35 1f 1a 14 10 gfil11 0x64 [7:0] 40 20 1a 14 12 gaussian filter register setting (for optional 400kbps) (hex) register address: bit bt=1.0 bt=0.5 bt=0.4 bt=0.3 bt=0.25 [1:0] 0 0 0 0 0 [3:2] 0 0 0 0 0 [5:4] 0 0 0 0 0 gfil00 0x59 [7:6] 0 0 0 0 0 [3:0] 0 0 0 0 0 gfil01 0x5a [7:4] 0 0 0 0 0 [3:0] 0 0 0 0 0 gfil02 0x5b [7:4] 0 0 0 0 1 gfil03 0x5c [7:0] 00 00 00 00 01 gfil04 0x5d [7:0] 00 00 00 01 03 gfil05 0x5e [7:0] 00 00 01 03 05 gfil06 0x5f [7:0] 00 00 02 07 09 gfil07 0x60 [7:0] 00 03 07 0c 0f gfil08 0x61 [7:0] 00 0b 10 14 15 gfil09 0x62 [7:0] 05 1d 1f 1d 1a gfil10 0x63 [7:0] 3c 35 2d 24 1f gfil11 0x64 [7:0] 7e 40 34 28 20
fedl7396a/b/e-07 ml7396a/b/e 78/140 programming fsk modulation by setting gfsk_en ([data_set;b0 0x47(4)]) =0b0, fsk modulation can be selected. in fsk modulation, fine frequency deviation can be set by [gfil00/fsk_fdev1:b0 0x59] to [gfil03/fsk_fdev4:b0 0x5c] registers. by setting [fsk_time1:b0 0x65] to [fsk_time4:b0 0x68] registers, fsk timing can be fine tuned. symbol register address function symbol register address function i fsk_fdev1 0x59 fsk_time1 0x65 ii fsk_fdev2 0x5a fsk_time2 0x66 iii fsk_fdev3 0x5b fsk_time3 0x67 iv fsk_fdev4 0x5c freq dev 33.4x2(hz) fsk_time4 0x68 modulation timing by 4mhz counter [note] 1. fsk modulation does not support optional 400kbps. + ? f - ? f output ?1? tx_pol=0b0 [ data _ set:b0 0x47 ( 6 ) ] output ?0? tx_pol=0b0 [data_set:b0 0x47(6)] iv iii ii i i ii iii iv
fedl7396a/b/e-07 ml7396a/b/e 79/140 programming data rate changing 50kbps, 100kbps, 200kbps and 400kbps data rate can be chnaged by rate[2:0] ([data_set:b0 0x47(2-0)]). when changing data rate, below registers may have to be changed. note: 1. depending on data rate, the following chage may not be necessary. for details, please refer to each register setting value corresponding to each data rate in "initial register setting" file. 2. please change data rate setting in trx_off state. [bank0] [rate_set1:b0 0x04] register (note: setting is necessary only when changing to 150kbps.) [rate_set2:b0 0x05] register (note: setting is necessary only when changing to 150kbps.) [if_freq_afc_h:b0 0x30] register [if_freq_afc_l:b0 0x31] register [bpf_afc_adj_h:b0 0x32] register [bpf_afc_adj_l:b0 0x33] register [tx_pr_len:b0 0x42] register [ch_space_fl:b0 0x4c] register [ch_space_fh:b0 0x4d] register [f_dev_l:b0 0x4e] register [f_dev_h:b0 0x4f] register [2div_search:b0 0x6f] register [bank1] [pll_cfp_adj:b1 0x09] register [if_freq_h:b1 0x0a] register [if_freq_l:b1 0x0b] register [if_freq_cca_h:b1 0x0c] register [if_freq_cca_l:b1 0x0d] register [bpf_adj_h:b1 0x0e] register [bpf_adj_l:b1 0x0f] register [bpf_cca_adj_h:b1 0x10] register [bpf_cca_adj_l:b1 0x11] register [bank2 registers] [rate_adj1:b2 0x2a] register (note: setting is necessary only when changing to 150kbps.) [rate_adj2:b2 0x2b] register (note: setting is necessary only when changing to 150kbps.)
fedl7396a/b/e-07 ml7396a/b/e 80/140 programming narrow band option setting by setting nbo_sel ([data_set:b0 0x47(7)]) = 0b1, narrow bandwidth mode can be selected. the narrow band mode is applying 200 khz channel spacing instead of 400 khz defined in ieee802.15.4g standard. when selecting the narrow bandwidth mode, below registers should be changed to narrow rx bandpass filter bandwidth. [bank0] [if_freq_afc_h:b0 0x30] register [if_freq_afc_l:b0 0x31] register [bpf_afc_adj_h:b0 0x32] register [bpf_afc_adj_l:b0 0x33] register [bank1] [pll_cfp_adj:b1 0x09] register [if_freq_h:b1 0x0a] register [if_freq_l:b1 0x0b] register [if_freq_cca_h:b1 0x0c] register [if_freq_cca_l:b1 0x0d] register [bpf_adj_h:b1 0x0e] register [bpf_adj_l:b1 0x0f] register [bpf_cca_adj_h:b1 0x10] register [bpf_cca_adj_l:b1 0x11] register
fedl7396a/b/e-07 ml7396a/b/e 81/140 rf adjustment pa adjustment ml7306 family has output circuits for 1mw and 20mw (10mw as well). output circuits can be selected by pa_sel ([pa_cntrl:b1 0x07(4)]). each output power can be adjusted with 16 resolutions by using [pa_adj1:b1 0x04] to [pa_adj3:b1 0x06] registers and [pa_reg_adj1:b1 0x33] to [pa_reg_adj3:b1 0x35] registers. in each register, 20mw circuit is adjusted by upper 4bits and 1mw circuit is adjusted by lower 4bits. 3 setting value can be stored for each output power circuit. applying setting can b e selected by pa_adj_sel[1:0] ([pa_cntrl:b1 0x07(1-0)]). when switching output power between 10mw and 20mw, 10mw adjustment setting valueis stored into [pa_adj1:b0 0x04] and those for 20mw is stored into [pa_adj2:b1 0x05]. after that, output power can be switched by pa_adj_sel[1:0] setting. maximum 3 settings can be stored for each output circuit. note: output impedance at pa_out pin (#27) differs between 1mw output circuit and 20mw output circuit. therefore, the most optimized matching circuit will also be different. following table shows setting validity corresponfding to pa_sel and pa_adj_sel[1:0] setting. pa adjustment registers pa regulator adjustment registers pa_adj1 pa_adj2 pa_adj3 pa_re g_adj1 pa_reg_ad j2 pa_reg_adj3 pa_sel (b1 0x07) pa_adj_sel [1:0] (b1 0x07) [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [2:0] [2:0] [2:0] 0b0 0b01 valid valid 0b0 0b10 valid valid 0b0 0b11 valid valid 0b1 0b01 valid valid 0b1 0b10 valid valid 0b1 0b11 valid valid
fedl7396a/b/e-07 ml7396a/b/e 82/140 i/q adjustment image rejection ratio can be adjusted by tuning iq si gnal balance. the adjustment procedure is as follows: 1. from sg, image frequency signal is input to ant pin (#30). input signal: no modulation.wave input frequency: channel frequency - (2 * if frequency) in case of 100kbps, if frequency = 720khz. please refer to the ?programing if frequency?. input level: -70dbm 2. by setting rssi_out ([rssi/temp_out:b1 0x03(0)]) =0b1, outputing rssi from a_mon pin (#24). 3. issuing rx_on by [rf_status:b0 0x6c] register, by adjusting [iq_mag_adj:b1 0x14] and [iq_phase_adj: b1 0x15] registers, finding setting value so that rssi value is minimum by measuring a_mon pin (#24). [i\q adjustment flow] start 1 power on initialize setting please refer to ?initial re g ister settin g ? file. rx_on issue [rf_status:b0 0x6c] 1 channel setting [ch_set:b0 0x6b] channel setting [ch_set:b0 0x6b] rssi output setting [rssi/temp_out:b1 0x03] sg output setting modulation: no modulation level : -70dbm frequency: ch frequency- 2 * if frequency end amplitude, phase valur confirm amplitude/phase re-adjustment by changing range. [iq_mag_adj] 3lsb [iq_phase_adj] 6lsb so that rssi value is minimum. set phase value [iq_phase_adj:b1 0x15] initial amplitude setting [iq_mag_adj:b1 0x14]=0x08 phase adjustment by [iq_phase_adj:b1 0x15], so that rssi value is minimum. amplitude adjustment by [iq_mag_adj:b1 0x14], so that rssi value is minimum. set amplitude value [iq_mag_adj:b1 0x14]
fedl7396a/b/e-07 ml7396a/b/e 83/140 vco adjustment in order to compensate vco operation ma rgin, optimized capacitance compensation value should be set in each operation frequency. this capacitance compensation value can be acquired by vco calibration. by performing vco calibration when power-up or reset, acquired capacitance compensation values for upper limit and lower limit of operation frequency range (for both tx/rx), based on this value optimised capacitance value is applied during tx/rx operation. lower limit frequency can be set by [vco_cal_min_fl:b1 0x16] to [vco_cal_min_fh:b1 0x18] registers. upper frequency is definced by [vco_cal_max_n:b1 0x19] register as frequency range. [vco adjustment flow] the following flow is the procedure for acquiring capacitance compensation value when power-up or reset. start setting lower limit frequency initialize setting [vco_cal_min_fl:b1 0x16] [vco_cal_min_fm:b1 0x17] [vco_cal_min_fh:b1 0x18] setting operation frequency range [vco_cal_max_n:b1 0x19] set v co_cal_start = 0b1 start calibration [vco_cal_start:b1 0x1d(0)] note: vco calibration should be performed only during idle state. end calibration operation no v co calibration completion? int[02] completion wait [int_source_grp1:b0 0x24] y es
fedl7396a/b/e-07 ml7396a/b/e 84/140 vco calibration is necessary every 0.9ms to 4.2ms. after completion, capacitance compensation values are stored in the following registers. capacitance compensation value at lower limit frequency: [vco_cal_min:b1 0x1a] capacitance compensation value at upper limit frequency: [vco_cal_max:b1 0x1b] in actual operation, based on the 2 compensation values, the mo st optimized capacitance value for the frequency is calculated and applied. the calculated value is stored in [vco_cal:b1 0x1c] register. by evaluation stage, if below values are stored in the mcu memory and uses these values upon reset or power-up, calibration operation can be omitted. registers to be saved in the mcu memory. [vco_cal_min_fl:b1 0x16] [vco_cal_min_fm:b1 0x17] [vco_cal_min_fh:b1 0x18] [vco_cal_max_n:b1 0x19] [vco_cal_min:b1 0x1a] [vco_cal_max: b1 0x1b] note: 1. for lower limit frequency, please use frequency at least 2mhz lower than operation frequency 2. for upper limit frequency should be selected so th at operation frequency is in the frequency range. 3. frequency range should not include 36mhz multiplied frequency, i.e. 900mhz, 936mhz. 4. in case of like a channel change, if the setting frequency is outside of calibration frequency range, calibration process has to be performed again with proper frequency. vco lower limit frequency setting as described in the ?programing channel #0 frequency?, vco lower limit frequency can be set by setting f-counter parameter into [vco_cal_min_fl:b1 0x16], [vco_cal_min_fm:b1 0x17] and [vco_cal_min_fh:b1 0x18] registers. n-counter and a-counter parametrs are applied the valu stored in [ch0_na:b0 0x4b] register. lower limit frequency setting value can be calculated using the following formula. low_f = {f low ? (4 * n + a) * f ref } / f ref * 2 20 (integer part) [note: using 20bit circuit] here low_f : lower limit frequency f-counter setting f low : lower limit frequency [mhz] f ref : pll reference frequency (input clock=36mhz) n : n-counter parameter a : a-counter parameter if operation low limit frequency is 923.1mhz, n= 6 and a=1. setting value should be lower than 2mhz. then in following example, lower limit frequency is set to 921.1mhz. (f ref = 36mhz) low_f = {921.1 ? (4 * 6 + 1) * 36mhz} /36mhz * 2 20 (integer part) = 614582 (0x960b6) setting values for each register is as follows: [vco_cal_min_fl:b1 0x16]= 0xb6 [vco_cal_min_fm:b1 0x17]= 0x60 [vco_cal_min_fl:b1 0x18]= 0x09
fedl7396a/b/e-07 ml7396a/b/e 85/140 vco upper limit frequency setting vco upper limit frequency is calculated as following formula, based on low limit frequency values and vco_cal_max_n[4:0] ([vco_cal_max_n: b1 0x19(5-0)]). vco calibration upper limit frequency = vco calibration lower limit frequency (b1 0x16-0x18) + f(b1 0x51) f is defined in the table below. vco_cal_max_n[4:0] ? f[mhz] 0b0_0000 1.125 0b0_0001 2.25 0b0_0011 4.5 0b0_0111 9 0b0_1111 18 0b1_1111 36 other than aboev prohibited
fedl7396a/b/e-07 ml7396a/b/e 86/140 energy detection value (ed value) adjustment [ed value adjustment] ed value is calculated by rssi signal (analog signal) from rf part,. by performing the following adjustment, it is possible to correct the variation in lsis. the gain adjustment and related registers are described below. in order to cover wider input range, gain should be changed at given point. threshold for gain change points are set by [gain_mtol:b1 0x1c] to [gain_mtoh:b0 0x1f]. [rssi_adj_m:b1 0x20] and [rssi_adj_l:b1 0x21] registers are used to addition values to maintain linearity when changing gain. rssi slope can be set to [rssi_val_adj:b1 0x23] register so that ed value can be between 0x00(min) and 0xff(max). for thse register setting, please use the value specified in the ?initial register setting? file. adjusting the input level variation for the same input level can be set to [rssi_adj:b1 0x02] register. it must compensate the slope before compensation defined by [rssi_val_adj:b1 0x23] register. however, if positive value is set , ed value cannot be decreased down to 0x00 at low input signal level. if ne gative value is set, ed value cannot be increased up to 0xff. ed value operation in the high gain range: rssi value>gain_htom, and move to middle gain. operation in the middle gain range: rssi value>gain_mtol, and move to low gain. gain_mtoh rssi value, and move to high gain. operation in the low gain range: gain_ltom rssivalue, and move to middle gain. low gain operation range [rssi_val_adj:b1 0x23] ed value [rssi_adj_l:b0 0x21] rf input level [rssi_adj_m:b0 0 x 20] [gain_htom:b0 0x1e] high low rssi value (adc output) middle gain operation range [gain_mtol:b0 0x1c] high gain operation range [gain_ltotom:b0 0x1d] [gain_mtoh:b0 0x1f] [ rssi adj:b1 0 x 02 ]
fedl7396a/b/e-07 ml7396a/b/e 87/140 other setting ber measurement setting the following registers setting are necessary for rx side when measuring ber. [pll_mon/dio_sel:b0 0x69] = 0x01 [demod_set:b1 0x01] = 0x80 [demod_set2:b2 0x0a] = 0x10 [sync_mode:b2 0x12] = 0x00
fedl7396a/b/e-07 ml7396a/b/e 88/140 flow charts initialization in initialization status, interrupt process, registers setting, vco calibration are necessary. (1) interrupt process upon reset, all interrupt notification settings ([int_en_grp1-4:b0 0x2a-0 x2d]) are enabled. after hard reset is released, int[00] (group 1: clock stabilization completion interrupt) will be detected. after int[00] notification, please mask unused interruput elements by using [int_en_grp1:b0 0x2a] to [int_en_grp4] registers. if interrupt elements are stored internnaly, interrupt will ge nerate as soon as interrupt is unmasked, unless clearing the interrpt. when clearing interrupt, it is recommended to clear interrput after masking the interrupt. (2) registers setting in reset value setting, clock is output from dmon pin (#17). if clock output is not used, please assign another monitoring function to dmon pin and terminate clock output. after hard reset is released, all registers are accesible ex cept for fifo access registers and bank1 registers before int[00] notification. (3) vco calibration executing vco calibration after setting upper and lower limit of the operation frequency range. operating frequency should be in the calibration frequency range. in case of usin g frequency which is outside of calibration frequency range, calibration process has to be performed again with proper frequency. during vco calibration, please register access is prohibited.
fedl7396a/b/e-07 ml7396a/b/e 89/140 start n o clock stabilization completion int. ? int[00] [int_source_grp1: b0 0x24] yes masking int[00] [int_en_grp1:b0 0x2a] int[00] clear (1)interrupt process [int_source_grp1:b0 0x24] masking unused interrupts [int_en_grp1:b0 0x2a] to [int_en_grp4:b0 0x2d] register setting (2)register setting (including clock output termination) end (3)vco calibration start vco calibration [vco_cal_start:b1 0x1d] n o vco calibration completion int. ? int[02] [int_source_grp1: b0 0x24] int[02] clear [int_source_grp1:b0 0x24]
fedl7396a/b/e-07 ml7396a/b/e 90/140 tx mode (dio mode) dio (tx) mode can be selected by setting dio_en ([pll_mon/dio_sel:b0 0x69(1)]) =0b1. in dio (tx) mode, when issuing tx_on command, data input to dio pin (#15) will be tr ansmitted to the air. tx data following sfd field should be input from host mcu and tx data should be synchronized with dclk from dclk pin (#16). after tx completion, trx_off commnand should be issued. tx data request accept completion interrupt (int[22] or int[23] group3) notification should be required to start dio (tx) transmission. before issuing tx_on command, writing dummy data to a fifo to generate tx data request accept completion interrupt. more than 4byte dummy data (excluding lngth field) is required. [example: setting minimum dummy packet] set crc_done ([fec/crc_sec:b0 0x46(0)]) =0b0, and write 0x00-01-02 (3byte) tp [wr_tx_fifo:b0 0x7e] register. note: the first tx data input during dio (tx) mode. initial status of dclk pin (#16) is ?l?. therefore there is no falling edge for the 1 st tx data, the 1 st tx data should be pre-set to dio pin (#15) before writing dummy packet. for more details, please refer to the explanation in following page.
fedl7396a/b/e-07 ml7396a/b/e 91/140 tx data corresponding to each register setting and dio input is as below: [example] transmitting pren 13757-4rev mode c format a packet (ml7396e) case 1: input tx data at rising edge of dclk [conditions] [preamble_set:b0 0x39] =0x55 [sfd1_set1:b0 0x3a] =0x55 [sfd1_set2:b0 0x3b] =0x55 [tx_pb_len:b0 0x42] =0x03 [rx_pr_len/sfd_len:b0 0x43] =0x02 case 2: input tx data at falling edge of dclk [conditions] [preamble_set:b0 0x39]=0xaa [sfd1_set1:b0 0x3a] =0xaa [sfd1_set2:b0 0x3b] =0xaa [tx_pb_len:b0 0x42] =0x03 [rx_pr_len/sfd_len:b0 0x42] =0x02 preamble syncword data dio input (syncword) dclk output dio input (data) tx data (air) register setting and dio input preamble_set (3byte) sfd1_set1 (1byte) sfd1_set2 (1byte) 0101010101 01010101 010101 01 010101 01 0101 01 00 0011 1101 0101 0100 1100 1101 xxxx ?. pre-set ? l ? to dio pin. these 2 bits will be transmitted as 1 st bi t and 2 nd bi t . sending data following last 3 bytes of syncword. preamble syncword preamble_set (3byte) sfd1_set2 (1byte) pre-set ? l ? to dio pin. this bit will be transmitted as 1 st bi t sending data following last 3 bytes of syncword. 101010101 01010101 0101010 1 0101010 1 0101 010 0 0011 1101 0101 0100 1100 1101 xxxx ?. sfd1_set1 (1byte) data dclk output tx data (air) register setting and dio input dio input (syncword) dio input (data)
fedl7396a/b/e-07 ml7396a/b/e 92/140 [flowchart] start * rx_fifo_mon ([pll_mon/dio_sel:b0 0x69(0)]) setting does not affect on dio (tx) mode operation. tx_on issue [rf_status:b0 0x6c] end no y es input tx data [dio pin (#15)] write dummy data to a fifo y es next packet tx? no y es no no y es tx data request accept completion int? [int_source_grp3:b0 0x26] clear tx data request accept completion interrupt [int_source_grp3:b0 0x26] packet header setting [preamble_set:b0 0x39] [sfd1_set1-4:b0 0x3a-3d] [tx_pr_len:b0 0x42] [rx_pr_len/sfd_len:b0 0x43] set dio_en =0b1 [pll_mon/dio_sel:b0 0x69(2) ] set ?l/h? to dio pin * set 1 st biy of tx data to the dio pin. * set crc_done ([fex/crc_set:b0 0x46(0)])=0b0 (disable) and write 0x00-01-02 to [wr_tx_fifo:b0 0x7e] register. * if issuing tx_on before writing dummy data, same result can be achieved * timing up to dclk output varies depending on preamble length, sfd length and data rate dclk output? [dclk pin (#16)] * tx data should be input at falling edge of dclk. tx completion? trx_off issue [rf_status:b0 0x6c]
fedl ml 7396a/b/e-07 7396a/b/e 93/140 rx mode (dio mode) dio (rx) mode can be selected by setting dio_en ([pll_mon/dio_sel:b0 0x69(1)]) =0b1 and rx_fifo_mon ([pll_mon/dio_sel:b0 0x69(1)]) =0b1. in dio (rx) mode, when issuing rx_on command, preamble and sfd detection will be started. after preamble and sfd are detected , rx data is output through dio pin (#15). rx data following sfd field are output and rx data should be read at rising edge of dclk from dclk pin (#16). after rx completion, trx_off commnand should be issued. like packet mode, preamble and sfd detection are done according to the settings of [preamble_set:b0 0x39], [sfd1_set1:b0 0x3a] to [sfd1_set4:b0 0x3d], [rx_pr_len/sfd_len:b0 0x43] and [sync_condition:b0 0x44] registers.after sfd is deteceted, sfd detection interrupt (int[11] group2) will generate. the first rx data is output at the first rising edge of dclk after sfd detection interrupt notification.(timing from sfd detection interrupt to the first dclk rising edge is 9 s at 100kbps setting.) start set dio_en =0b1 rx_fifo_mon =0b1 [pll_mon/dio_sel:b0 0x69(1,0) ] detect condition setting * like packet mode, detect pattern should be set to ([preamble_set:b0 0x39] and [sfd_set1-4:b0 0x3a-3d] registers. [preamble_set:b0 0x39] [sfd1_set1-4:b0 0x3a-3d] [rx_pr_len/sfd_len:b0 0x43] [sync_condition:b0 0x44] note: different from dio (tx) mode setting. rx_on issue [rf_status:b0 0x6c] end no y es y es no dclk output? * afetr entering rx_on state, dclk will be output regardless of rx data. [dclk pin (#16)] read rx data * rx data should be read at rising edge of dclk. [dio pin (#15)] tx completion? trx_off issue [rf_status:b0 0x6c]
fedl7396a/b/e-07 ml7396a/b/e 94/140 tx mode (packet mode, packet length 256byte) packet mode can be selected by setting dio_en ([pll_mon /dio_sel:b0 0x69(1)]) =0b0. in packet mode, each tx data is written into a fifo by [wr_tx_fifo:b0 0x7e] register. after writing full tx data of a packet, issuing tx_on command. following pb (preamble), sfd data, tx data is transmitted to the air. when crc is enabled, the crc calcuration will be done automatically and crc result is set to fcs field and transmitted to the air. after tx completion interrupt (int[16]/[17] group3) occurs, the interrupt must be cleared. if the next tx packet is sent, the next tx packet data is written to a fifo. if rx is expected after tx, rx_on should be issued by [rf_status:b0 0x6e] register. tx can be terminated by issuing trx_off by [rf_status:b0 0x6e] register. at every packet writing, fifo0 and fifo1 are switched automatically. (fifo0 fifo1 fifo0)
fedl7396a/b/e-07 ml7396a/b/e 95/140 start tx fifo trigger level setting if the tx data length is shorter than the fast_tx trigger level, tx will start by writing all data to a fifo. [tx_alarm_lh:b0 0x35] =0x00 [tx_alarm_hl:b0 0x36] =0x00 write tx data to fifo [wr_tx_fifo:b0 0x7e] from cca flowchart no tx_on iisue [rf_status:b0 0x6c] tx completed (int[16]/int[17])? [int_source_grp3:b0 0x26] clear interrupts [int_source_grp3:b0 0x26] int[16],[22] or int[17],[23] rx_on issue [rf_status:b0 0x6c] go to rx flowchart rf state transition completion int? [int_source_grp2:b0 0x25] int[10] cca execution? go to cca flowchart if random back-off period specified in the ieee, go to cca normal mode. if idle is detected in minimum period, go to cca idle detection mode. cca result=busy? no tx data request accept completion int? [int_source_grp3:b0 0x26] y es y es auto_rx_en =0b1? [auto_ack_set:b0 0x55(6)] and send ack request packet? go to rx flowchart y es no no y es cca continue? clear tx data request [intsource_grp3:b0 0x6c] or [pd_data_req:b0 0x28] trx_off iisue [rf_status:b0 0x6c] no end y es write tx data to fifo [wr_tx_fifo:b0 0x7e] y es no y es next packet t x ? no y es no rx? trx_off issue [rf_status:b0 0x6c] end
fedl7396a/b/e-07 ml7396a/b/e 96/140 tx mode (packet mode, packet length 257byte) the host mcu should write tx data to a fifo while checking fifo-full interrupt (int[05] group1) and fifo-empty interrupt (int[04] group1) in order to avoid fifo-overrun or fifo-underrun. other operation are same as packet mode (less than 256byte). enabling fast_tx mode by setting auto_tx ([packet_mode_set:b0 0x45(2)] =0b1 and fast_tx_trg[7:0] ([fast_tx_set:b0 0x6a(7-0)], tx will start when data amount written to a fifo exceeds the setting value of fast_tx_trg[7:0]. start fast_tx setting when sending ack request packet, please set auto_rx_en =0b1. auto_tx ([packet_mode_set:b0 0x45(2)])=0b1 fast_tx trigger: [fast_tx_set:b0 0x6a] ([auto_ack_set:b0 0x55(6)]) tx fifo trigger level lh: [tx_alarm_lh: b0 0x35] tx fifo trigger level hl: [tx_alarm_hl:b0 0x36] if data amount written to a fifo exceeds the fast_tx_trg[7:0], tx will start. write tx data to fifo [wr_tx_fifo:b0 0x7e] end no clear interrupts int[16],[22] or int[17].[23] [int_source_grp3:b0 0x26] y es y es no y es no fifo-empty (int[04])? [int_source_grp1:b0 0x24] *total data amount should be the size subtracting crc length from the length value. write tx data to fifo [wr_tx_fifo:b0 0x7e] if too much tx data written to a fifo, aftert tx completion interrupt, issue trx_off and then issue phy reset. clear int[04] [int_source_grp1:b0 0x24] tx data request accept completion int? (int[22] or int[23]) [int_source_grp3:b0 0x26] y es tx completion(int[16]/[17])? [[int_source_grp3:b0 0x 26] go to rx flowchart y es no auto_rx_en =0b1? [auto_ack_set:b0 0x55(6)] and send a ck request packet? write tx data to fifo [wr_tx_fifo:b0 0x7e] no next packet t x ? set auto_tx=0b0 [paket_mode_set: b0 0x45(2)]
fedl7396a/b/e-07 ml7396a/b/e 97/140 tx mode (ack receiving with address filter) even when address filtering function is enabled, ack packet (or beacon packet) will be received. however dscarding ack packet can be set by rx_ack_cancel ([auto_ack_set:b0 0x55(7)]) =0b1. and when auto_rx_en ([auto_ack_set:b0 0x55(6)])=0b1, the ack packet just after transmitting ack request packet can be received without discarding. start address filtering setting: [addfil_cntrl:b2 0x60] rx_ack_cancel ([auto_ack_set:b0 0x55(7)] =0b1 auto_rx_en ([auto_ack_set:b0 0x55(6)] =0b1 end note: ack packet is detected by frame type only. therefore even if the first ack packet destination is different address, this ack packet will be received. the following process is as below; address match following 2 nd packet will be discarded. address mismatch by setting rx_ack_cancel=0b0, maintain rx until receiving ack packet with right address.
fedl7396a/b/e-07 ml7396a/b/e 98/140 rx mode (packet mode, packet length 256 bytes) packet mode can be selected setting dio_en ([pll_mon /dio_sel:b0 0x69(1)]) =0b0. in dio mode, when issuing rx_on command, preamble and sfd detection will be started. after preamble and sfd are detected, rx data will be stored into a fifo. after rx completion interrupt (int[18]/[19] group3) occurs, the host mcu will read rx data from [rd_rx_fifo:b0 0x7f] register. if crc error interrupt (int[20]/ [21]) is generated, fifo data has to be cleared by setting (fifo_clr1/0 ([int_source _grp1:b0 0x26(7/6)]) =0b0. after clearing rx retaive interrpts, if receiving the next packet, maintain rx_on status and waiting for next rx completion interrupt. if tx is expected after rx, tx_on should be issued by [rf_status:b0 0x6e] register. if terminating rx, issuing trx_off by [rf_status:b0 0x6e] register. if fifo-full trigger and fifo-empty trigger are not used, please set 0x00 to both [rx_alarm_lh:b0 0x37]) and [rx_alarm_hl:b0 0x38)] registers. start rx fifo trigger level setting [rx_alarm_lh:b0 0x37] =0x00 [rx_alarm_hl:b0 0x38] =0x00 rx_on issue [rf_status:b0 0x6c] from automatic ack receive in tx mode [note] if crc_en ([fec/crc_set:b0 0x46(3)])=0b0, read out all rx data from a fifo before issuing trx_off command. please refer [fec/crc_set:b0 0x46] register y es no set ack_stop =0b1 [auto_ack_set:b0 0x55(0) ] no no rx completion (int[18]/[19])? [int_source_grp3:b0 0x26] y es y es go to crc error flowchar t in ?error process? crc error (int[20]/int[21])? [int_source_grp3:b0 0x26] auto_rx_en=0b1? [auto_ack_set] b0 0x55 read rx data from fifo set ack_stop =0b0 [rd_rx_fifo:b0 0x7f] [auto_ack_set:b0 0x55(0) ] y es go to act tx mode flowchart ack r e q u e s t ? ( 256byte) no y es no no end tx? trx_off issue [rf_status:b0 0x6c] clear interrupts int[18],[20] or int[19].[21] [int_source_grp3:b0 0x26] next packet rx? go to tx flowchart
fedl7396a/b/e-07 ml7396a/b/e 99/140 rx mode (packet mode, packet length 257 bytes) the host mcu should read rx data from a fifo while checking fifo-full interrupt (int[05] group1) and fifo-empty interrupt (int[04] group1) in order to avoid fifo-overrun or fifo-underrun. other operation are same as packet mode (less than 256byte). start rx_on issue [rf_status:b0 0x6c] y es no y es no fifo-full (int[05])? [int_source_grp1:b0 0x24] clear int[05] [int_source_grp1 b0 0x24] read rx data from fifo [rd_rx_fifo:b0 0x7f] no ack r e q u e s t ? y es rx completion (int[18]/[19])? [int_source_grp3:b0 0x26] gp to ack tx mode flowchart y es go to crc error flowchar t in ?error process? crc error (int[20]/int[21])? [int_source_grp3:b0 0x26] read rx data from fifo [rd_rx_fifo:b0 0x7f] clear interrupts int[18],[20] or int[19].[21] [int_source_grp3:b0 0x26] next packet rx? no y es no tx? go to tx flowchart end trx_off issue [rf_status:b0 0x6c]
fedl7396a/b/e-07 ml7396a/b/e 100/140 rx mode (ieee802.15.4d mode) when using ieee80.15.4d mode by ieee_mode ([packet_mode_set:b0 0x45(1)]) =0b0, basic flowchart is same as ieee 802.15.4g. however reading 1byte dummy data should be requ ired after reading amount of data given by length field. start rx_on issue [rf_status:b0 0x6c] no y es no y es rx completion (int[18]/[19])? [int_source_grp3:b0 0x26] y es crc error (int[20]/int[21])? go to crc error flowchar t in ?error process? [int_source_grp3:b0 0x26] no read rx data from fifo [rd_rx_fifo:b0 0x7f] y es no read all data from fifo read dummy data (1byte) from fifo [rd_rx_fifo:b0 0x7f] clear interrupts int[18],[20] or int[19].[21] [int_source_grp3:b0 0x26] next packet rx? trx_off issue [rf_status:b0 0x6c] end
fedl7396a/b/e-07 ml7396a/b/e 101/140 ack tx mode (auto_ack, packet length 256 bytes) when auto_ack function is enabled by auto_ack_en ([auto_ack_set:b0 0x55(4)]) =0b1, if receiving tx packet with ack request, preparing tx ack packet (tx_on) or tr ansmitting ack packet automatically (when using ack timer). start set auto_ack_en=0b1 [auto_ack_set:b0 0x55(4)] no a ddress match? rx_on issue [rf_status:b0 0x6c] y es from rx flowchart ( 256 byte) phy reset issue read pending data no y es [rst_set:b0 0x01] rx completion (int[18]/[19])? [int_source_grp3:b0 0x26] no crc error (int[20]/int[21])? [int_source_grp3:b0 0x26] y es read rx data from fifo [rd_rx_fifo:b0 0x7f] clear int[20] or [21] [int_source_grp3:b0 0x26] phy reset issue [rst_set:b0 0x01] set ack_stop=0b1 [auto_ack_set:b0 0x55(0)] set ack_stop=0b0 [auto_ack_set:b0 0x55(0)] end (*1) set ack_stop=0b1 [auto_ack_set:b0 0x55(0)] when cca_auto_en=0b1, ([cca_cntrl:b0 0x15(7)]) executing cca automatically. (*1) set ack_stop=0b0 [auto_ack_set:b0 0x55(0)] ack frame setting end [ack_frame1:b0 0x53] [ack_frame2:b0 0x54] no auto ack ready (int[24])? [int_source_grp4:b0 0x27] y es when using ack timer, no need to set ack_send bit. set ack_send=0b1 [auto_ack_set:b0 0x55(1)] no tx completion? (int[16]/[17]) [int_source_grp3:b0 0x26] y es clear interrupts int[16],[22] or int[17].[23] [int_source_grp3:b0 0x26] set ack_stop=0b1 [auto_ack_set:b0 0x55(0)] (*1) (*1) only when data rate is 50kbps and sclk speed is 16mhz (max), please set 12 s wait between ack_stop=0b1 to ack_stop=0b0. set ack_stop=0b0 [auto_ack_set:b0 0x55(0)] end
fedl7396a/b/e-07 ml7396a/b/e 102/140 ack tx mode (auto_ack, packet length 257 bytes) start set auto_ack_en=0b1 [auto_ack_set:b0 0x55(4)] rx fifo trigger level setting [rx_alarm_lh:b0 0x37] =0x00 [rx_alarm_hl:b0 0x38] =0x00 y es crc error (int[20]/int[21])? [int_source_grp3:b0 0x26] rx_on issue [rf_status:b0 0x6c] no clear int[20] or [21] read pending data [int_source_grp3:b0 0x26] no y es fifo-full (int[05])? [int_source_grp1:b0 0x24] phy reset issue [rst_set:b0 0x01] from rx flowchart ( 257 byte) read rx data from fifo [rd_rx_fifo:b0 0x7f] phy reset issue [rst_set:b0 0x01] set ack_stop=0b1 [auto_ack_set:b0 0x55(0)] set ack_stop=0b0 [auto_ack_set:b0 0x55(0)] end (*1) set ack_stop=0b1 [auto_ack_set:b0 0x55(0)] (*1) set ack_stop=0b0 no a ddress match? [auto_ack_set:b0 0x55(0)] y es end ack frame setting no auto ack ready (int[24])? [int_source_grp4:b0 0x27] [ack_frame1:b0 0x53] [ack_frame2:b0 0x54] y es when using ack timer, no need to set ack_send bit. set ack_send=0b1 [auto_ack_set:b0 0x55(1)] no tx completion? (int[16]/[17]) [int_source_grp3:b0 0x26] rx completion? no (int[18]/[19]) y es [int_source_grp3:b0 0x26] clear interrupts y es int[16],[22] or int[17].[23] [int_source_grp3:b0 0x26] set ack_stop=0b1 [auto_ack_set:b0 0x55(0)] (*1) (*1) only when data rate is 50kbps and sclk speed is 16mhz (max), please set 12 s wait between ack_stop=0b1 to ack_stop=0b0. set ack_stop=0b0 [auto_ack_set:b0 0x55(0)] end
fedl7396a/b/e-07 ml7396a/b/e 103/140 ack tx mode (without auto_ack) below flowchart shows the ack packet transmission without auto_auk function. by using fifo-full interrupt (int[05] gtoup1), the host mcu write ack packet to a fifo during rx. after rx completion, transmitting ack paket. start rx_on issue [rf_status:b0 0x6c] no y es if using interrupt notification by sint pin (#10), pleas unmask int[05] by [int_en_grp1:b0 0x24] register. rx fifo trigger level setting [rx_alarm_lh:b0 0x37] =0x00 [rx_alarm_hl:b0 0x38] =0x00 no address match? y es fifo-full (int[05])? force_trx_off issue [int_source_grp1:b0 0x24] [rf_status:b0 0x6c] read rx data from fifo [rd_rx_fifo:b0 0x7f] read length and address field. set ack packet to a fifo. write tx data to fifo [wr_tx_fifo:b0 0x7e] clear fifo [int_source_grp1:b0 0x24] no y es rx completion (int[18]/[19])? end [int_source_grp3:b0 0x26] no y es crc error (int[20]/int[21])? [int_source_grp3:b0 0x26] ack packet cancellation clear pd_data_req tx_on issue [rf_status:b0 0x6c] (set 0b0) [pd_data_req:b0 0x28(1,5] phy reset issue [rst_set:b0 0x01] no tx completion? (int[16]/[17]) [int_source_grp3:b0 0x26] y es trx_off issue [rf_status:b0 0x6c] read rx data from fifo [rd_rx_fifo:b0 0x7f] read out remaining rx data. end
fedl7396a/b/e-07 ml7396a/b/e 104/140 address filter when address filtering function is enabled, if receiving packet which address field are mismatch, packet discard completion interrupt (int[03] group1) will be generated. at this time, if addfil_ng_set ([packet_mode_set:b0 0x45(5)]) =0b0, aborting packet data immediately after address mismatch detection and crc error interrupt (int[20]/[21] group3) is also generated at the same time. (the details of interrupt notifiaction, please refer to the [interrupts timing when using int_tim_ctrl] in ?address filtering function?.) after notifying packet discard completion interrupt and crc error interrupt, it is need to clear fifo by [int_source_grp1:b0 0x24] register or reading out data specified by lngth field from the fifo, in order to store next packet to right fifo. after that, clearing packet discard completion interrupt and crc error interrupt, and then waiting next packet. start rx_on issue [rf_status:b0 0x6c] no for deteils of process after receiving ack packet, please refer [auto_ack_set:b0 0x55] register description (*4) and tx mode (ack receiving with addrsss filter) flowchart. address filtering setting addfil_ng_set=0b0 (b0 0x45(5)) [addfil_cntrl:b2 0x60] [panid_l/h:b2 0x61,62] [64addr1-8:b2 0x63-6a] [sht_addr0_l/h:b2 0x6b,6c] [sht_addr1_l/h:b2 0x6d.6e] packet discard completion? (int[03]) [int_source_grp1:b0 0x24] y es read rx data from fifo [rd_rx_fifo:b0 0x7f] clear interrupts int[18],[20] or int[19].[21] [int_source_grp3:b0 0x26] next packet rx? no end trx_off issue [rf_status:b0 0x6c] y es no rx completion? (int[18]/[19]) [int_source_grp3:b0 0x26] y es no crc error? confirming fifo filed which crc error occurs. (int[20]/[21]) [int_source_grp3:b0 0x26] y es if addfil_ng_set=0b1, when packet discard cpmletion is generated, phy reset should be required. clear fifo which crc error occurs [int_source_grp1:b0 0x24 (7 or 6)] if crc error interrupt occurs at the same time, following process is same as described in the flowchart . clear interrupts int[03] [int_source_grp1:b0 0x24] int[20] or int[21] [int_source_grp3:b0 0x26 [note] when executing phy reset during address filtering function, any interrupt procedure should be done. when executing phy reset, if reading data is remaining in a fifo, this data will also be cleard and discarded packet counter is reset to 0.
fedl7396a/b/e-07 ml7396a/b/e 105/140 fifo clear (rx) when rx completion interrupt (int[18]/[19] group3) and crc error interrupt (int[20]/[21] group 3) is notified in the same time, clearing fifo by set 0b0 to fifo_clr0/1 ([int_source_grp1:b0 0x24(6/7)]) if no need to read remaining rx data. and then clearing rx completion interript and crc error interrupt. if receiving next packet, keeping rx_on state. if termin ating rx_on state, please issueing trx_off command by [rf_status:b0 0x6c] register. be sure to clear the correct fifo bank only. alternatively, fifo can be cleared by issueing phy reset by using [rst_set:b0 0x01] register. start rx fifo trigger level setting [rx_alarm_lh:b0 0x37] =0x00 [rx_alarm_hl:b0 0x38] =0x00 rx_on issue [rf_status:b0 0x6c] no fifo-full (int[05])? [int_source_grp1:b0 0x24] y es read rx data from fifo [rd_rx_fifo:b0 0x7f] no y es rx completion (int[18]/[19])? [int_source_grp3:b0 0x26] crc error (int[20]/int[21])? [int_source_grp3:b0 0x26] n o read rx data from fifo [rd_rx_fifo:b0 0x7f] y es clear fifo [int_source_grp1:b0 0x24(6,7)] no y es read out rx data alternatively issueing phy reset. clear interrupts n ote: int[18],[20] or int[19].[21] be sure to clear the correct fifo bank. [int_source_grp3:b0 0x26] when issuing phy reset, both fifos are cleard. next packet rx? trx_off issue [rf_status:b0 0x6c] end
fedl7396a/b/e-07 ml7396a/b/e 106/140 sleep set 0b1 to sleep_en ([clk_set:b0 0x02(5)]) in order to enter into sleep state. sleep state can be released by setting sleep_en=0b0. start slee p execution set sleep_en=0b1 [clk_set:b0 0x02(5)] no y es sleep release? slee p release set sleep_en=0b0 [clk_set:b0 0x02(5)] clock stabilization completion? (int[00]) no [int_source_grp1:b0 0x24] y es end
fedl7396a/b/e-07 ml7396a/b/e 107/140 ed scan ed value will be automatically acquired by issuing rx_on by [rf_status:b0 0x6c] register after setting ed_calc_en [ed_cntrl:b0 0x1b(7)]) =0b1. ed values is constantly updated when ed_calc_en=0b1 during rx_on state. when changing rf channel, once set ed_calc_en=0b0 and set 0b1 again after rf channel change completion. except for rf channel change, please do not set 0b0 to ed_calc_en bit. start set ed_calc_en=0b1 [ed_cntrl:b0 0x1b(7)] rx_on issue [rf_status:b0 0x6c] these processes are not necessary i f 250 s wait is added after rf channel changing setting. no y es ed_done=0b1? [ed_cntrl:b0 0x1b(4)] ed value will be constantly updated read ed value [ed_rslt:b0 0x16] y es rf channel change? rf channel change [ch_set:b0 0x6b] the timing from rf channel change setting to channel change completion is 100 s. no following operation this timing should be considered. end trx_off issue [rf_status:b0 0x6c] set ed_calc_en=0b0 [ed_cntrl:b0 0x1b(7)] set ed_calc_en=0b1 [ed_cntrl:b0 0x1b(7)]
fedl7396a/b/e-07 ml7396a/b/e 108/140 cca operation normal mode cca normal mode will be executed by issueing rx_on by [rf_status:b0 0x6c] register after setting cca_en ([cca_cntrl:b0 0x15(4)])=0b1, cca_idle_en ([cca_cntrl:b0 0x15(3)])=0b0 and cca_loop_start ([cca_cntrl:b0 0x15(5)])=0b0. compariing acquired ed average value with cca threshold value in [cca_level:b0 0x13] register and notice the result. after cca execution, cca_en is turned disabled, and rf maintains rx_on state. even if set cca_en=0b1 during rx_on state, cca can be performed by. however, in this case, 16 s - 32 s (2 cycle of a/d conversion) wait is automatically added as the filter stabilization period before cca execution. (if cca_en=0b1 is set before issuing rx_on, wait is not added because filter stabilization period is included in rf transition period.) if bit synchronization is detected during cca, keep receivi ng with wider bpf bandwidth for cca operation. if cca is executed after bit synchronization detection, cca is executed with normal bpf bandwidth. cca execution is also possible during diversity search. in th is case, after cca completion diversity search will be resumed automatically. start n o yes n o yes cca setting [cca_cntrl:b0 0x15(5-3)] cca_loop_start=0b0 cca_en=0b1 cca_idle_en=0b0 rx_on issue cca start [rf_status:b0 0x6c] cca completion (int[08])? [int_source_grp2:b0 0x25] read cca_rslt[1:0] [cca_cntrl:b0 0x15(1-0)] set cca_en=0b1 [cca_cntrl:b0 0x15(4)] clear int[08] [int_source_grp2:b0 0x25] stop cca? trx_off issue [rf_status:b0 0x6c] end
fedl7396a/b/e-07 ml7396a/b/e 109/140 continuous mode cca continuous mode will be executed by issueing rx_on by [rf_status:b0 0x6c] register after setting cca_en ([cca_cntrl:b0 0x15(4)])=0b1, cca_idle_en ([cca_cntrl:b0 0x15(3)])=0b0 and cca_loop_start ([cca_cntrl:b0 0x15(5)])=0b1. in this mode, cca continues until cca_loop_stop ([cca_cntrl:b0 0x15(6)]) =0b1 is set. in this mode, cca_done ([cca_cntrl: b0 0x15(2)]) will not be 0b1 and cca completion interrupt (int[08] group2) is not generated. during cca execution, cca_rslt[1:0] ([cca_cntrl:b0 0x15(1-0)]) and cca_prog[9:0] ([cca_prog_l/h:b0 0x19(7-0)/1a(1-0)]) are cons tantly updated. the value will be kept by setting cca_loop_stop=0b1. start cca setting [cca_cntrl:b0 0x15(5-3)] cca_loop_start=0b1 cca_en=0b1 cca_idle_en=0b0 * cca result can be read during cca. note: cca results before rx_on are invalid. (last value). please read the valu after rx_on and ed_done=0b1. cca start rx_on issue [rf_status:b0 0x6c] * rf state transition (rx_on) completion can be confirmed by [rf_statu:b0 0x0b] = 0x66 no rx_on completion (int[10]) ? [int_source_grp2:b0 0x25] y es no y es ed_done=0b1? [ed_cntrl:b0 0x1b(4)] no y es stop cca? cca sto p set cca_loop_stop=0b1 [cca_cntrl:b0 0x15(4)] read cca result cca_rslt[1:0] ([cca_cntrl:b0 0x15(1-0)]) cca_prog[9:0] ([cca_prog_l/h:b0 0x19/1a]) end trx_off issue [rf_status:b0 0x6c]
fedl7396a/b/e-07 ml7396a/b/e 110/140 idle detection mode cca is continuously executed until idle is detected. cca (idle detection mode) will be executing by setting rx_on by [rf_status:b0 0x6c] register after setting cca_en ([cca_cntrl:b0 0x15(4)])=0b1, cca_idle_en ([cca_cntrl:b0 0x15(3)])=0b1 and cca_loop_start ([cca_cntrl:b0 0x15(5)])=0b0.. start cca setting [cca_cntrl:b0 0x15(5-3 )] cca_loop_start=0b0 cca_en=0b1 cca_idle_en=0b1 cca start rx_on issue [rf_status:b0 0x6c] no cca completion (int[08]) ? [int_source_grp2:b0 0x25] y es: idle detection clear int[08] [int_source_grp2:b0 0x25] end
fedl7396a/b/e-07 ml7396a/b/e 111/140 in the below condition, cca (idle detection mode) will be executed automatically. 1. when set 0b1 to ting cca_auto_en ([cca_cntrl:b0 0x15(7)]), cca (idle detection mode) will be executed after receiving ack request packet. internal operation is colored yellow start set cca_auto_en=0b1 [cca_cntrl:b0 0x15(7)] rx_on issue [rf_status:b0 0x6c] receiving packet with ack request * please refer to the ?auto_ack function?. rx completion no automatic execution cca (idle detection mode) execution no cca completion (int[08]) ? [int_source_grp2:b0 0x25] y es cca result should be read to determine cca completion interrupt occues by idle detection or cca abort timer completion. cca_rslt[1:0]=0b00? [cca_cntrl:b0 0x15(1-0)] y es: idle detection clear int[08] clear int[08] [int_source_grp2:b0 0x25] [int_source_grp2:b0 0x25] automatic execution tx_on issue end auto ack ready interrupt (int[24]) generation [int_source_grp4:b0 0x27] end
fedl7396a/b/e-07 ml7396a/b/e 112/140 2. when address filtering function is enabled by set 0b1 to one of bit4-0 in [addfil_cntrl:b2 0x60] register, and if addfil_idle_det ([packet_mode_set:b0 0x45(0)]) =0b1, cca (idle detection mode) will be executed after discardingrx data. internal operation is colored yellow start address filtering setting [packet_mode_set:b0 0x45(0)] [addfil_cntrl:b2 x60(4-0)] rx_on issue [rf_status:b0 0x6c] receiving packet with unmatched address * please refer to the ?address filtering function? packet discard completion interrupt (int[03]) generation [int_source_grp1:b0 0x24] automatic execution cca (idle detection mode) execution no * crc error interrupt (int[20]/[21] group3) may be generated. for details of interrupt timing, please refer to the ?address filtering function?. cca completion (int[08]) ? [int_source_grp2:b0 0x25] y es clear int[08] [int_source_grp2:b0 0x25] end
fedl7396a/b/e-07 ml7396a/b/e 113/140 2 diversity operation after setting 2div_en ([2div_cntrl: b0 0x71(0)])=0b1, i ssuing rx_on by [rf_status:b0 0x6c] register. antennas are switched to acquire each ed value, the antenna with higher ed value will be automatically selected. ml7396 supports recovering function from incorrect diversity completion caused by errornous detection due to thermal noize, after dicersity search completion, if preamble can not be detected until antenna search timer expiration, ml7396 judges the previous diversity search comple tion is incorrect and resume diversity operation automatically. when resume diversity operation for next packet receiving, pl ease clear rx completion interrupt (int[18]/[19] group3) and diversity search completion interrupt (int[09] group2) . for details, please refer to ?diversity function?. ed values ([ant1_ed:b0 0x73], [ant2_ed:b0 0x74] registers) from diversityantennas and the diversity result ([2div_rslt:b0 0x72(1-0)]) will be cleard when clearing divers ity search completion interrpy, clearing rx completion or diversity resume by errornous detection. ed values and diversity result should be read before clearing rx completion interrupt. start set 2div_en=0b1 [2div_cntrl:b0 0x71(0)] masking int[09] [ int en gr p2:b 0 0 x2b ] * if set 2div_en=0b1 after issuing rx_on, diversity will be executed after search timer completion defined by [2div_search:b0 0x6f] register. rx_on issue if sfd is detected while seatch timer counting, diversity will not be executed and keep receiving. [rf_status:b0 0x6c] no rx completion (int[18]/[19])? [int_source_grp3:b0 0x26] y es read diversity result [2div_rslt:b0 0x72(1-0)] [ant1_ed:b0 0x73] [ant2_ed:b0 0x74] clear int[18] or [19] [int_source_grp3:b0 0x26] clear int[09] [int_source_grp2:b0 0x25] y es * diversity search completion interrupt (int[09] group2) should be cleard at same timing of rx completion interrupt clearance. next packet rx? no trx_off issue [rf_status:b0 0x6c] end
fedl7396a/b/e-07 ml7396a/b/e 114/140 cca operation during diversity if cca is executed during diversity operation, there is a case cca_done ([cca_cntrl:b0 0x15(2)]) is not notified and keep cca operation. when executing cca during diversity, set cca-competion wait timer (case1), or once disabling diversity before cca execution (case 2). case 1: set cca completion wait timer start set 2div_en=0b1 [2div_cntrl:b0 0x71(0)] masking int[09] [ int en gr p2:b 0 0 x2b ] in ieee standard, random buck off time is required to resume cca. however, ml7396 family does not have rundum back off time generator. rx_on issue [rf_status:b0 0x6c] set cca_en=0b1 [cca_cntrl:b0 0x15(4)] cca completion (int[08])? [int_source_grp2:b0 0x25] no y es cca start cca-completion wait timer start no cca-completion wait timer expiration? y es set cca_en=0b0 [cca_cntrl:b0 0x15(4)] read cca_rslt[1:0] [cca_cntrl:b0 0x15(1-0)] clear int[08] [int_source_grp2:b0 0x25] resume cca? yes n o end
fedl7396a/b/e-07 ml7396a/b/e 115/140 case 2: disbleing diversity before cca execution start set 2div_en=0b1 [2div_cntrl:b0 0x71(0)] masking int[09] [ int en gr p2:b 0 0 x2b ] rx_on issue [rf_status:b0 0x6c] set cca_en=0b1 [cca_cntrl:b0 0x15(4)] wait receiving packet set 2div_en=0b0 [2div_cntrl:b0 0x71(0)] * alternatively, 1. force_trx_off issue 2. set cca_en b1 =0 3. rx_on issue phy reset issue [rst_set:b0 0x01] in ieee standard, random buck off time is required to resume cca. however, ml7396 family does not have rundum back off time generator. forced antenna setting during cca set tx_ant_en [2div_rslt:b0 0x72(5)] set cca_en=0b1 [cca_cntrl:b0 0x15(4)] no cca completion (int[08])? [int_source_grp2:b0 0x25] y es cca operation read cca_rslt[1:0] [cca_cntrl:b0 0x15(1-0)] clear int[08] [int_source_grp2:b0 0x25] y es resume cca? n o end
fedl7396a/b/e-07 ml7396a/b/e 116/140 error process crc error case 1: crc error occurs due to bit error if crc error occurs due to bit error, no need to read out rx data from fifo. by issuing phy reset by [rst_set:b0 0x01] register or fifo clear by [int_source_grp1:b0 0x 24] register, receiving status can be maintained. for details of fifo clear, please refer to ?fifo clear? in ?flow charts?. case 2: out-of-sync detection after sfd detection (during length, data, crc field receiving) if out-of-syn is detected after sfd detection, crc error interrupt (int[20]/[21] group3) will be notified. however rx completion interrput (int[18]/[19] group3) will not be generated. if this case occurs, read rx data that amount is specified length field from fifo and then clearing crc error interrpt. start rx_on issue [rf_status:b0 0x6c] rx completion (int[18]/[19])? [int_source_grp3:b0 0x26] y es crc error notification ([int[20]/[21]] [int_source_grp2:b0 0x25] crc error notification ([int[20]/[21]] [int_source_grp2:b0 0x25] read rx data from fifo [rd_rx_fifo:b0 0x7f] read all rx data? phy reset issue [rst_set:b0 0x01] or clear int[20] or [21] [int_source_grp3:b0 0x26] no y es clear int[20]/[21] [int_source_grp3:b0 0x26] from rx flowchart y es no note: be sure to clear the correct fifo bank. when issuing phy reset, both fifos are cleard. next packet rx? no trx_off issue [rf_status:b0 0x6c] end
fedl7396a/b/e-07 ml7396a/b/e 117/140 tx fifo access error if one of the following conditions is met, tx fifo access error interrupt (int[15] group2) will be generated. the 3 rd packet data is written to a fifo when the transmitting data remain in both fifo0 and fifo1. data write overflow occurs to a fifo. no tx data in the tx_fifo during tx data transimission. when tx fifo acccess error interrupt occurs, issuing trx_off after tx completion interrupt(int[16]/[17] group3) is recognized, or issueing force_trx_off by [rf_status:b0 0x0a] register without waiting for tx completion interrupt. after that, clearing tx completion interru pt and tx fifo access error interrrput.. if tx fifo access error occurs, subquent tx data will be inverted. crc error should be detected at rexeiver side even if trx_off is issued when tx completion interrupt detected. start tx setting [fast_tx_set:b0 0x6a] auto_tx=0b1 [packet_mode_set:b0 0x45(2)] [tx_alarm_lh:b0 0x35 [tx_alarm_hl:b0 0x36] tx fifo access error? int[15] [ i n t s o u rce g r p 2 : b0 0 x2 5 ] write tx data to fifo [wr_tx_fifo:b0 0x7e] * if data written to fifo exceed fast_tx_trg[7:0] in [fast_tx_set:b0 0x6a] register, tx will start. (length is included in the data length written to fifo) no y es normat tx go to tx flowchart terminate tx immediatel y ? no tx completion (int[16]/[17])? [int_source_grp3:b0 0x26] no y es y es auto_tx=0b0 [packet_mode_set:b0 0x45(2)] trx_off issue [rf_status:b0 0x6c] force_trx_off issue [rf_status:b0 0x6c] clear int[16] or [17] [int_source_grp3:b0 0x26] clear int[15] [int_source_grp2:b0 0x25] end trx_off issue [rf_status:b0 0x6c] next packet t x ? no y es no y es phy reset issue [rst_set:b0 0x01] auto_tx=0b0 [packet_mode_set:b0 0x45(2)] a uto_tx has been set?
fedl7396a/b/e-07 ml7396a/b/e 118/140 rx fifo access error if one of the following conditions is met, rx fifo access error interrupt (int[14] group2) will be generated. receiving the 3 rd packet when the receiving data remain in both fifo0 and fifo1. rx data overflow occurs to rx_fifo (overrun) read rx_fifo during no data in the rx_fifo (underrun) when rx fifo access error interrupt occurs, after rx completion interrupt (int[18]/[19] group3) is recognized, issuing phy reset by [rst_set:b0 0x01] regi ster or fifo clear by [int_source_grp1:b0 0x24] register. after that, cleari ng rx completion interrupt and rx fifo access error interrupt. after receiving 2 packets, by setting clk1_en ([clk_set:b0 0x02(1)] = 0b0, rx fifo access error can be avoid. start rx setting [rx_alarm_lh:b0 0x37] [rx_alarm_hl:b0 0x38] rx_on issue [rf_status:b0 0x6c] refer to rx flowchart rx process (packet mode) rx fifo access error notification int[14] [int_source_grp2:b0 0x25] phy reset issue [rst_set:b0 0x01] or clear fifo [int_source_grp1:b0 0x24] when interrupt caused by overrun, or underrun, fifo clear is possible. clear interrupts int[18],[20] or int[19].[21] [int_source_grp3:b0 0x26] clear interrupts int[14] [int_source_grp2:b0 0x25] end trx_off issue [rf_status:b0 0x6c] next packet t x ? y es no
fedl7396a/b/e-07 ml7396a/b/e 119/140 pll unlock detection tx during tx, if pll unlock is detected, pll unlock interrupt (int[25] group4) will be generated. when pll unlock interrupt occurs, force_trx_off is automati ccally issued and move to idle state. before next tx operation, issuing phy reset by [rst_set:b0 0x01] register and clearing pll unlock interrupt should be required. internal operation is colored yellow start write tx data to fifo [wr_tx_fifo:b0 0x7e] tx_on issue [rf_status:b0 0x6c] no pll unlock (int[25])? [int_source_grp4:b0 0x27] y es normat tx go to tx flowchart automatic execution force trx_off issue phy reset issue [rst_set:b0 0x01] clear int[25] [int_source_grp4:b0 0x27] y es next packet t x ? no end
fedl7396a/b/e-07 ml7396a/b/e 120/140 rx durin g rx, if pl l un lock is de tected, p ll u nlo ck i nterru pt (int[2 5] g ro up 4) w ill be g ene rated. durin g r x, ev en if pll un lock is detected, rx _on st ate is ma in ta in ed (do no t move t o id le st ate). be for e ne xt rx op er at io n, i ss ui ng ph y r ese t b y [ rst _s et :b 0 0x01] reg is ter an d cleari ng pll unl oc k i nt erru pt sh oul d be required. start rx _on is su e [rf _s ta tus :b0 0x6c ] no pl l u nloc k (in t[25])? [i nt _so urce_ grp4:b 0 0 x2 7] y es phy r ese t issu e normat rx [rs t_s et :b0 0x0 1] go to rx fl owchar t clea r i nt [25] [i nt _sou rce_gr p4:b 0 0 x2 7] y es nex t p ac ket rx ? no end
fedl7396a/b/e-07 ml7396a/b/e 121/140 data rate change sequence when changing data rate during operation, data rate should be set in trx_off state. issuing modem reset by [rst_set: b0 0x01] register is required after data rate change. if not is suing modem reset, ml7396 can not transmit or receive correctlly. tx_on or rx_on state start trx_off issue [rf_status:b0 0x6c] * relating registers are as below; changing data rate [data_set:b0 0x47] [rate_set1:b0 0x04] [rate_set2:b0 0x05] modem reset issue [rst_set:b0 0x01] end
fedl7396a/b/e-07 ml7396a/b/e 122/140 timing chart the followings are operation timing of major functions. [note] bold characters indicate pins relative signals. non bold characters indicate internal signal. start up regfulator voltage wake up time 660 s resetn osc enable reg. enable clk_init_done v dd 1.5ms clock stabilization time from sleep state int[00] interrupt [int_source_grp1:b0 0x24] sintn spi access possible whole operation possible spi access possible except for bank1 and fifo rf operation possible (rf regulator stabilization time)
fedl7396a/b/e-07 ml7396a/b/e 123/140 tx conditions ? symbol rate: 100 kbps ? preamble length: 4 byte ? sfd length: 2 byte ? length: 2 byte ? crc: 8 bit (1 byte) ? data length: 100 byte ? ramp control: on * lamp control timing can be adjusted by the [2div_gain_cntrl:b0 0x6e], [rx_on_adj2:b1 0x3f] and [tx_off_adj1:b1 0x55] registers. for more details, please refer to the ?ramp control function?. tx_on command trx_off command set_trx[3:0] = 0b1001 set_trx[3:0] = 0b1000 fifo write ([rf_status:b0 0x6c(3-0)]) trx_off(idle) tx_on rf status pll enable pa enable (pa_on) data enable air trx_off(idle) tx complete pd_data_cfm0/1 [pd_data_req:b0 0x28] 18 s 44.4 s [pa_on_adj:b2 x1e] 52 s 3 s 55 s 348 s scen ([rf_status:b0 0x6c(3-0)]), sintn int[16]/int[17] interrupt [int_source_grp3:b0 0x26] int[22]/int[23] interrupt [int_source_grp3:b0 0x26] tx enable (tx_on) 27 s 6 s (num tx symbol +3) * symbol duration ((4+2+2+100+1)*8+3)*10 s = 8,750 s host mcu interrupt processing period int[10] interrupt [int_source_grp2:b0 0x25] int[10] interrupt [int_source_grp2:b0 0x25]
fedl7396a/b/e-07 ml7396a/b/e 124/140 rx (without cca) conditions ? symbol rate: 100 kbps ? preamble length: 4 byte ? sfd length: 2 byte ? length: 2 byte ? crc: 8 bit (1 byte) ? data length: 100 byte ? ramp control: on trx_off command rx_on command set_trx[3:0] =0b1000 ([rf_status:b0 0x6c(3-0)]) set_trx[3:0] =0b0110 ([rf_status:b0 0x6c(3-0)]) read fifo dat trx_off(idle) rx_on rf status pll enable rx enable trx_off(idle) data rx complete pd_data_ind0/1 [pd_ a_ind: b0 0x29] 18 s 6 s 2*8*10 s=160 s rxd enable demodulated data fifo write enable pb sfd length data crc (100+1)*8*10 s=8,080 s fifo read enable (spi to fifo) rx data can be read from a fifo. the last data can be read after pddata_ind0/1=0b1. the shortest read out time will be approx 8,240 s+ 16 sclk cycles from sfd detection (int[11] , group2). psdu fileld data is stored into fifo (byte by byte) scen sintn int[18]/int[19] or int[20]/int[21] [int_source_grp3: b0 0x26] int[11] interrupt [int_source_grp2: b0 0x25] 2 s 1 s 115.5 s (17.78 s+[rx_on_adj:b2 0x22]) 1.11 s [rxd_adj:b2 0x24] int[10] interrupt [int_source_grp2:b0 0x25] int[10] interrupt [int_source_grp2:b0 0x25]
fedl7396a/b/e-07 ml7396a/b/e 125/140 rx (with cca) conditions ? symbol rate: 100 kbps ? preamble length: 4 byte ? sfd length: 2 byte ? length: 2 byte ? crc: 8 bit (1 byte) ? data length: 100 byte ? ramp control: on trx_off command rx_on command set_trx[3:0] =0b1000 set_trx[3:0] =0b0110 ([rf_status:b0 0x6c(3-0)]) read fifo ([rf_status:b0 0x6c(3-0)]) scen _ trx_off(idle) rx_on rf status pll enable rx enable trx_off(idle) data rx complete pddata_ind0/1 [pd data_ind:b0 0x29] 18 s 6 s 2*8*10 s=160 s rxd enable demodulated data pb sfd length data crc fifo write enable (100+1)*8*10 s=8,080 s fifo read enable (spi to fifo) rx data can be read from a fifo. the last data can be read after pd_data_ind0/1=0b1. the shortest read out time will be approx 8,240 s+ 16 sclk cycles from sfd detection (int[11], group2). cca enable sintn psdu field data is stored into fifo(byte by byte) int[8] interrupt [int_source_grp2:b0 0x25] 2 s 1 s 1.11 s [rxd_adj:b2 0x24] 115.5 s (17.78 s+[rx_on_adj:b2 0x22]) int[18]/int[19] or int[20]/int[21] interrupt [int_source_grp3:b0 0x26] cca completion data can be received even during cca. int[10] interrupt [int_source_grp2:b0 0x25] int[10] interrupt [int_source_grp2:b0 0x25] int[11] interrupt [int_source_grp2: b0 0x25]
fedl7396a/b/e-07 ml7396a/b/e 126/140 transition from tx to rx condition: ? ramp control: on scen r d p r transition from rx to tx mode condition: ? ramp control: on tx_on rx_on f status ata enable a_enable 3 s 53 s x enable 97.68 s [rx_on_adj:b2x22] sintn tx enable 48 s 1.1 s int[10] interrupt [int_source_grp2:b0 0x25] tx_on command set_trx[3:0] =0b1001 ( [ rf status:b0 0x6c ( 3-0 )] ) scen rf status rx_on tx_on rx enable pa enable data enable 3 s 44.4 s [pa_on_adj:b2 0x1e] 30 s tx enable 10 s sintn 1.1 s int[10] interrupt [int_source_grp2:b0 0x25]
fedl7396a/b/e-07 ml7396a/b/e 127/140 transition from tx to sleep condition: ? ramp control: on sleep command sleep_en ( [clk_set:b0 0x02 ( 5 ) ] ) =0b1 transition from rx to sleep condition: ? ramp control: on s r r p o r rx_on trx_off (automatic transition) f status x enable ll enable 3 s 6 s leep enable sc enable 9 s eg. enable 9 s switch to sub-regulator scen sintn int[10] interrupt [int_source_grp2:b0 0x25] sleep command sleep_en ([clk_set:b0 0x02(5)]) =0b1 1.1 s tx_on trx_off (sleep) rf status pa enable tx enable 54 s 348 s pll enable 6 s sleep enable osc enable 9 s reg. enable 9 s scen switch to sub-regulator sintn 1.1 s int[10] interrupt [int_source_grp2:b0 0x25]
fedl7396a/b/e-07 ml7396a/b/e 128/140 transition from sleep to idle sleep exit command sleep_en ([clk_set:b0 0x02(5)]) =0b0 scen note: when using tcxo, enabling tcxo (clock) before issuing sleep exit command. if enabling tcxo after issuing sleep exit command, the start time will delay for a certain time. transition from idle to sleep sleep enable rf status osc enable reg. enable clk_init_done reg_init_done note: if disabling tcxo during sleep, wait more than 4 s after issuing sleep command, then disabling tcxo (clock). trx_off sleep command sleep_en ([clk_set:b0 0x02(5)]) = 0b1 scen sintn trx_off rf status 660 s sleep enable osc enable reg. enable clk_init_done reg_init_done 1500 s baseband operation possible (fifo and rf control register can be set) rf operation possible rf stabilization time from sleep state. clock stabilization time from sleep state spi access possible sintn int[00] interrupt [int_source_grp1:b0 0x24]
fedl7396a/b/e-07 ml7396a/b/e 129/140 vco calibration calibration start command vc_cal_start ([vco_cal_start:b1 0x1d (0)]) =0b1 vco_cal_sta vcal interrupt clk_init_done 870 to 4160 s rf regulator wake up time. ? from sleep 1.1ms ? from idle 0ms sintn calibration period scen reg_init_done int[02] interrupt [int_source_grp1:b0 0x24]
fedl7396a/b/e-07 ml7396a/b/e 130/140 about fcc support ml7396a (915mhz band) complies with fcc part 15. when the outputpowe is -1dbm or less, part 15.249 is applied, and when the output power is +30dbm or less, part 15.247 is applied. spurious emissions should comply with part 15.209. part 15.247 requires the frequency hopping or the wideband digital modulation. for details of the frequency hopping, please refer to the "about frequency hopping" below. for details of th e wideband digital modulation, please refer to the " initial reg ister setting " file. about frequency hopping (fhss: fr equency hopping spread spectrum) according to the fcc (united states radio act) part 15.247, the fhss system which 20db bandwidth is less than 250 khz, should have 50 or more hopping channels. if 20db bandwidth is 250 khz or more, 25 or more hopping channels should be supported. and the channel occupation time should be limited to 400ms at a maximum. the following examples show how to control and set registers in order to comply with above regulations. for details of register settings, please refer to the "initial registers setting" file. ? frequency switch flow during tx (0) tx completion (tx_on) (1) transition to trx_off or rx_on state by set_trx[3:0] ([rf_status:b0 0x6c(3-0)]). (2) switching frequency by [ch0_fl:b0 0x48], [ch0_fm:b0 0x49] and [ch0_fh:b0 0x4a] registers. (3) issuing tx_on command by set_trx[3:0]. repeat (0) to (3). ? frequency switch flow during rx (0) rx completion (rx_on) (1) masking pll unlock interrupt by in t_en[25] ([int_en_grp4:b0 0x2d(1)]) =0b0. (2) switching frequency by [ch0_fl:b0 0x48], [ch0_fm:b0 0x49] and [ch0_fh:b0 0x4a] registers. (3) wait 100 s. (pll lock period) (4) clear the pll unlock interrupt (int[25] group4), and enable the interrupt by int_en[25] =0b1 (5) receive data repeat (0) to (5). * pll unlock interrupt may be detected during frequency switch. it is recommended to masking the pll unlock interrupt for 100 s during frequency switch as shown in (1) to (4). the following examples show how to control the frequency hopping system. ?control example 1. tx equipment transmits a long term preambl e, and the rx equipment scans channels to detect a preamble tx equipment hops the frequency according to the hopping pattern. and the channel occupation time should be less than 400ms to comply with the regulation. rx equipment does not know the using channel transmitting preamble, and so scans all channels for detecting preamble. the preamble transmitting period should be longer than the channel scan period on the rx equipment. for details of the channel scan flow, please refer to the flow chart shown later. the one channel scan time can be calculated as "preamble search period (36bits / data rate) + pll lock period (100 s)". the following table shows the channel scan period for each data rate. please set an appropriate preamble length according to th e following table. the preamble length can be set by [tx_pr_len:b0 0x42] register. (max. 255 bytes)
fedl7396a/b/e-07 ml7396a/b/e 131/140 table. channel scan period for each data rate required period for 255 byte pb required period for data rate all channels scan availability transmitting period one channel scan [ms] [kbps] [ms] [ms] 25ch 50ch 25ch 50ch 10 204.0 3.70 92.5 185.0 20 102.0 1.90 47.5 95.0 40 51.0 1.00 25.0 50.0 50 40.8 0.82 20.5 41.0 100 20.4 0.46 11.5 23.0 150 13.6 0.34 8.5 17.0 200 10.2 0.28 7.0 14.0 400 5.1 0.19 4.8 9.5 * this table does not take into account the register access time. * this control method cannot be applied under the "" condition, since the all channel scanning period exceeds the preamble transmission period. control example 1 flowchart. start set preamble [tx_pr_len:b0 0x42] hop? transmit data receive data no y es no transmit? receive? y es no channel scan y es switch frequency
fedl7396a/b/e-07 ml7396a/b/e 132/140 details of channel scan flow. channel scan start masking pll unlock interrupt [int_en_grp4:b0 0x2d(1)] set frequency [ch0_fl:b0 0x48] [ch0_fm:b0 0x49] [ch0_fh:b0 0x4a] reset modem [rst_set:b0 0x01(1) wait (36 bits / data rate + 100 s) clear/enable pll unlock interrupt [int_source_grp4:b0 0x27(1)] [int_rn_grp4:b0 0x2d(1)] detect preamble? [phy_state:b0 0x0f(5)] no y es end of channel scan
fedl7396a/b/e-07 ml7396a/b/e 133/140 ? control example 2. use beacon for synchronization and common hopping pattern in this example, both master and slave nodes use the same synchronized hopping pattern. the master node periodically transmits a beacon on pre-defined channel. the slave node receives the beacon for synchronizing the hopping pattern. the slave node waits for a beacon at the pre-defined channel. once completing synchronization, both nodes hop frequencies according to the common hopping pattern. the hopping interval shoul d be ?the beacon interval di vided by the number of hopping channels? and required less than 400ms. when transmitting, the transmitting period should be calculated from the data length, making sure to avoid spanning hopping intervals. when using multiple hopping patterns, adding sequential number s (pattern number) on each hopping pattern. and the master node attaches the using pattern number into a beacon. this hopping method is available regardless of the data rate, the diversity search setting, and the number of hopping channels.
fedl ml 7396a/b/e-07 7396a/b/e 134/140 [master node flowchart] starting start set the beacon transmitting channel set the hopping pattern number ye s beacon timer expiration? n o ye s hopping timer expiration? n o wait until the next hopping timing tr a n s mi t da t a re ce i ve da t a ye s data send period < remaining time before the hopping timer expiration? n o ye s transmit? ye s n o receive? n o hopping ye s hopping timer ex p iration? beacon transmission n o
fedl7396a ml73 /b/e-07 96a/b/e 135/140 [slave node flowchart] starting start set the beacon receiving channel ye s beacon timer expiration? n o ye s hopping timer expiration? n o wait until the next hopping timing tr a n s mi t da t a re ce i ve da t a ye s data send period < remaining time before the hopping timer expiration? n o ye s transmit? ye s n o receive? n o hopping ye s hopping timer ex p iration? n o beacon received? n o ye s
fedl7396a/b/e-07 ml7396a/b/e 136/140 application circuit example here is a circuit example for 915mhz/920mhz, 13dbm, and up to 200kbps. 10 f decoupling capacitor should be pl aced to common 3.3v power pins . murata lqw15series inductors are recommended. for more details about designing information, please refer to the ?ml7396 family lsis hardware design manual?. 915mhz 920mhz l1 4.3nh 3.9nh c1 3.9pf 4.3pf lpf1 dea160915lt-5038a 0 ? (tdk)
fedl7396a/b/e-07 ml7396a/b/e 137/140 package dimensions remarks for surface mount type package surface mount type package is very sensitive affected by heating from reflow process, humidity during storaging therefore, in case of reflow mounting process, please contact sales representa tive about product name, package name, number of pin, package code and required reflow process condition (reflow method, temperature, number of reflow process), storage condition.
fedl7396a/b/e-07 ml7396a/b/e 138/140 footprint pattern (recommendation)
fedl7396a/b/e-07 ml7396a/b/e 139/140 revision history page document no. date previous edition current edition description fedl7396 a be-01 2013.02.27 ? ? initial release ( draft version ) fedl7396a_b_e-02 to -06 ? ? ? these versions are not released. fedl7396 a b e-07 2015.01.15 ? ? official release ( base on fjdl7396a b e-07 )
fedl7396a/b/e-07 ml7396a/b/e 140/140 notes no copying or reproduction of this document, in part or in whole, is permitted without the consent of lapis semiconductor co., ltd. the content specified herein is subject to change for improvement without notice. examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage an d operations of the products. the peripheral conditions must be taken into account when designing circuits for mass production. great care was taken in ensuring the accuracy of the informatio n specified in this document. however, should you incur any damage arising from any inaccuracy or misprint of such information, lapis semiconductor shall bear no responsibility for such damage. the technical information specified herein is intended only to show the typical functions of and examples of application circui ts for the products. lapis semiconductor does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by lapis semiconductor and other parties. lapis semiconductor shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. the products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). the products specified in this document are not designed to be radiation tolerant. while lapis semiconductor always makes efforts to enhance the quality and reliability of its products, a product may fail or malfunction for a variety of reasons. please be sure to implement in your equipment using the products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any product, such as derating, redundancy, fire control and fail-safe designs. lapis semiconductor shall bear no responsibility whatsoever for your use of any product outside of the prescribed scope or not in accord ance with the instruction manual. the products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of h uman injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-react or controller, fuel-controlle r or other safety device). lapis semiconductor shall bear no responsibility in any way for use of any of the products for the abo ve special purposes. if a product is intended to be used for any such special purpose, please contact a rohm sales representative before purchasing. if you intend to export or ship overseas any product or techno logy specified herein that may be controlled under the foreign exchange and the foreign trade law, you will be required to obtain a license or permit under the law. copyright 2013-2015 lapis semiconductor co., ltd. 2-4-8 shinyokohama, kouhoku-ku, yokohama 222-8575, japan http://www.lapis-semi.com/en/

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